High-Resistance Silicon Layer via Segmented Interface Grain Boundaries
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Solution Overview
Problem
The reliability of devices containing silicon layers with high resistance is compromised due to variations in conductivity between silicon layers fabricated using the same implantation process on different wafers, as reducing dopant amounts to achieve high resistance leads to inconsistent results.
Innovation Solution
A silicon layer with high resistance is fabricated by forming multiple silicon material layers with interface layers in between, where the dopant amount is controlled between 1*10^14 to 5*10^15 ions/cm2, and the grain boundaries of the upper silicon material layer are altered by forming a distinct interface layer, increasing total resistance and reducing conductivity variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the amount of dopants implanted is decreased to achieve high resistance, then the resistance increases, but the variations of conductivity between silicon layers become larger
Solution Approach 1:
The silicon layer is divided into multiple silicon material layers with interface layers between them. Each layer is doped separately with controlled dopant amounts (1×10^14 to 5×10^15 ions/cm²), and the interface layers create different grain boundaries. This segmentation allows each layer to contribute to high resistance while the cumulative effect reduces conductivity variations across wafers.
Solution Approach 2:
Different regions of the silicon layer structure are given different properties through the interface layers, which create distinct grain boundaries between silicon material layers. This local differentiation in grain boundary structure ensures consistent resistance characteristics across multiple wafers while maintaining high overall resistance.
2Manufacturing precision
If the amount of dopants implanted is decreased to achieve high resistance, then the resistance increases, but the reliability of devices containing these silicon layers becomes poor
Solution Approach 1:
The silicon layer is divided into multiple silicon material layers with interface layers between them. Each layer is doped separately with controlled dopant amounts (1×10^14 to 5×10^15 ions/cm²), and the interface layers create different grain boundaries. This segmentation allows each layer to contribute to high resistance while the cumulative effect reduces conductivity variations across wafers.
Solution Approach 2:
Different regions of the silicon layer structure are given different properties through the interface layers, which create distinct grain boundaries between silicon material layers. This local differentiation in grain boundary structure ensures consistent resistance characteristics across multiple wafers while maintaining high overall resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of devices by stabilizing the conductivity of silicon layers across different wafers, improving the overall performance and consistency of the silicon layer.
Implementation Method 1
the fabrication method of a silicon layer is to perform a chemical vapor deposition (CVD) process to form a silicon material layer, followed by performing an ion implantation process to implant dopants therein
Implementation Method 2
the fabrication method of a silicon layer is to perform a chemical vapor deposition (CVD) process to form a silicon material layer
Data Source
AI summary
A silicon layer with high resistance is provided. The silicon layer with high resistance is positioned on a substrate. Also, the silicon layer with high resistance includes a plurality of silicon material layers, and an interface layer between every two of the silicon material layers, wherein, the silicon material layers and the interface layer have dopants therein. The amount of implanted dopants is about 1*1014˜5*1015 ions/cm2, and the silicon material layers have different grain boundaries.