High-Resistivity SOI Substrate With Implanted Isolation Region
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Solution Overview
Problem
Current methods for preparing semiconductor-on-insulator (SOI) wafers are time-consuming, costly, and lack suitable thickness uniformity, especially for layers thinner than a few microns.
Innovation Solution
A method involving implanting As+ or O+ ions into a single crystal semiconductor handle substrate to form an isolation region, followed by depositing a dielectric layer and bonding a donor substrate to create a bonded structure with improved resistivity and reduced parasitic coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to prepare SOI wafers, then the process is simple, but the method is time-consuming and costly with poor thickness uniformity
Solution Approach 1:
The patent applies preliminary action by forming the isolation region through ion implantation into the handle substrate before the layer transfer process. This pre-formed isolation region enables better thickness control during subsequent thinning operations, achieving superior thickness uniformity without extending the overall process time significantly.
Solution Approach 2:
The patent changes physical parameters by using ion implantation to modify the electrical properties of the handle substrate, creating a high-resistivity isolation region. This parameter change (resistivity) enables better control over the layer transfer process and improves thickness uniformity while maintaining process efficiency.
2Reliability
If conventional SOI preparation methods are used, then the process is straightforward, but parasitic coupling is not reduced
Solution Approach 1:
The patent applies local quality by creating a localized isolation region with modified electrical properties (high resistivity) at specific depths in the handle substrate. This localized modification reduces parasitic coupling between devices while maintaining the overall simplicity of the SOI fabrication process, thereby improving device performance without significantly increasing process complexity.
Solution Approach 2:
The isolation region formed by ion implantation acts as an intermediary layer between the handle substrate and the device layer. This intermediary region with high resistivity properties reduces parasitic coupling and improves device performance while adding minimal complexity to the overall fabrication process.
3Reliability
If no isolation region is formed, then the process is simpler, but resistivity is insufficient and parasitic coupling increases
Solution Approach 1:
The patent replaces mechanical doping methods with ion implantation to form the isolation region. This substitution achieves the desired high resistivity more efficiently and with better control, improving reliability while actually reducing overall process complexity by eliminating the need for more complex mechanical doping equipment and procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves high resistivity in the handle wafer, reducing parasitic coupling and enhancing device performance by embedding a thin isolation region under the surface of the semiconductor handle substrate.
Implementation Method 1
implanting As+ or O+ ions into a single crystal semiconductor handle substrate to form an isolation region
Implementation Method 2
depositing a dielectric layer
Implementation Method 3
bonding a donor substrate to create a bonded structure
Data Source
AI summary
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and an isolation region that impedes the transfer of charge carriers along the surface of the handle substrate and reduces parasitic coupling between RF devices.