High Resistivity Substrate RF Noise Reduction
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Solution Overview
Problem
The high cost of manufacturing RF front-end modules (FEM) due to the expensive SOI substrate and SIP/MCM process limits the reduction of manufacturing costs, and existing RF modules face challenges in reducing RF noise coupling and improving electrical characteristics.
Innovation Solution
A semiconductor device is developed using a high resistivity silicon substrate with a deep trench device isolation region and a low concentration well region to surround transistors, which includes a gate structure, source and drain regions, and high concentration impurity regions, reducing RF noise coupling and improving electrical characteristics by extending depletion regions and reducing junction capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If SOI substrate is used to reduce RF noise coupling, then RF noise coupling is reduced, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive SOI substrates with conventional low-resistivity silicon substrates, using a cost-effective alternative material that achieves the same RF noise reduction function through different structural mechanisms (deep trench isolation and deep well regions instead of buried oxide layer)
Solution Approach 2:
The patent changes the substrate resistivity parameter from high-resistivity (SOI) to conventional low-resistivity silicon, and compensates by adjusting other parameters such as increasing trench depth and creating deep well regions to achieve equivalent or superior RF noise coupling reduction
2Adaptability or versatility
If SIP/MCM process is used for RF module manufacturing, then device integration is achieved, but manufacturing cost increases
Solution Approach 1:
The patent creates a universal fabrication process that works with conventional silicon substrates, allowing the same manufacturing steps to produce both standard digital devices and RF devices, thereby eliminating the need for specialized SIP/MCM processes while maintaining integration capabilities
Solution Approach 2:
The patent merges RF device fabrication with standard CMOS digital device fabrication processes, combining previously separate manufacturing flows into a single unified process that produces both device types on the same substrate using identical fabrication steps
3Object-affected harmful factors
If deep trench device isolation region is formed deeper than deep well region, then RF noise coupling is reduced, but device complexity increases
Solution Approach 1:
The patent segments the device isolation into two distinct parts: deep trench isolation extending through the substrate and shallow trench isolation at the surface level. This segmentation allows each trench type to perform its specific function optimally while maintaining overall structural simplicity
Solution Approach 2:
The patent extends the deep trench isolation into the vertical dimension, making it deeper than the deep well region, thereby utilizing the depth dimension to achieve RF noise reduction without increasing lateral structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces RF noise coupling and manufacturing costs, enhances RF switch performance by lowering off-state capacitance and on-state resistance, and improves heat dissipation efficiency, making it suitable for use in RF modules.
Implementation Method 1
extending depletion regions and reducing junction capacitance
Implementation Method 2
reducing junction capacitance
Implementation Method 3
improves heat dissipation efficiency
Data Source
AI summary
A semiconductor device includes a high resistivity substrate, a transistor formed on the high resistivity substrate, and a deep trench device isolation region formed in the high resistivity substrate to surround the transistor. Particularly, the high resistivity substrate has a first conductive type, and a deep well region having a second conductive type is formed in the high resistivity substrate. Further, a low concentration well region having the first conductive type is formed on the deep well region, and the transistor is formed on the low concentration well region.


