High Resistivity Substrate RF Noise Isolation

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Solution Overview

Problem

The high cost of manufacturing RF modules due to the expensive SOI substrate and SIP/MCM process limits the reduction of manufacturing costs for RF FEMs, which are essential in various wireless devices.

Innovation Solution

A semiconductor device is developed using a high resistivity substrate with a deep trench device isolation region and shallow trench device isolation regions to surround transistors, reducing RF noise coupling and improving electrical characteristics, while also using well regions and high concentration impurity regions to enhance performance and connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If SOI substrate is used to reduce RF noise coupling, then RF noise coupling is reduced, but manufacturing cost increases

Engineering Contradiction:
ImproveRF noise couplingVSAvoidmanufacturing cost
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent replaces expensive SOI substrates with conventional silicon substrates that have high resistivity regions formed through doping processes. This substitution uses cheaper, more readily available materials while achieving the same RF noise reduction function through alternative means (high resistivity regions instead of buried oxide layers).

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the electrical parameters of the silicon substrate by creating high resistivity regions through controlled doping. By modifying the resistivity parameter in specific areas, the substrate achieves RF noise isolation properties similar to SOI without requiring the expensive silicon-oxide-silicon structure.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If SIP/MCM process is used to manufacture RF module, then device integration is achieved, but manufacturing cost increases

Engineering Contradiction:
Improvedevice integrationVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent makes the conventional silicon substrate serve multiple functions: it provides mechanical support, electrical isolation through high resistivity regions, and a platform for forming transistors and other RF devices. This multi-functionality eliminates the need for complex SIP/MCM assembly processes while maintaining device integration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the functions of substrate support, electrical isolation, and device formation into a single conventional silicon substrate structure. By combining these functions that would otherwise require separate components in SIP/MCM architecture, the patent simplifies manufacturing while maintaining integration.

Inventive Principle:
Principle #5Merging (Combining)

3Object-affected harmful factors

If high resistivity substrate with deep trench isolation is used, then RF noise coupling is reduced, but device complexity increases

Engineering Contradiction:
ImproveRF noise couplingVSAvoiddevice structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent segments the silicon substrate into regions of different resistivity: high resistivity regions for RF noise isolation and lower resistivity regions for device formation. This segmentation allows the device to achieve RF noise reduction without requiring complex three-dimensional structures or multiple material layers.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9755068B2Semiconductor device and radio frequency module formed on high resistivity substrate
Publication Date: 2017.09.05 DONGBU HITEK CO LTD
  • US9755068B2 patent drawing
  • US9755068B2 patent drawing
  • US9755068B2 patent drawing

AI summary

In embodiments, a semiconductor device includes a high resistivity substrate, a transistor disposed on the high resistivity substrate, and a deep trench device isolation region disposed in the high resistivity substrate to surround the transistor. Particularly, the high resistivity substrate has a first conductive type, and a deep well region having a second conductive type is disposed in the high resistivity substrate. Further, a first well region having the first conductive type is disposed on the deep well region, and the transistor is disposed on the first well region.