High-Side Driver Circuit with Clamped Detection for Dead Time Control
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Solution Overview
Problem
Existing driver circuits for power semiconductor devices face issues with high power loss and potential malfunctions due to noise, particularly when using level shifter circuits that cause current to flow unnecessarily and misinterpret gate voltage changes, leading to shoot-through currents and difficulty in setting optimal dead time.
Innovation Solution
A driver circuit design that includes a high side and low side output transistor in series, with detection transistors and a clamping circuit to manage voltage changes, and logic circuits to control the on/off signals, reducing power loss and preventing malfunctions by optimizing dead time and isolating noise effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a level shifter circuit is used to shift gate voltage levels for high side output transistor control, then the driver circuit can operate with output voltage higher than gate breakdown voltage, but transmission delay times vary and dead time must be increased, making high speed switching difficult
Solution Approach 1:
The patent introduces a bootstrap capacitor as an intermediary energy storage element that couples the low-side reference potential circuit to the high-side reference potential circuit. This capacitor mediates the voltage level transition by storing energy at the low side and transferring it to the high side, enabling high side transistor control without direct high voltage signal transmission, thus reducing delay while maintaining voltage capability
Solution Approach 2:
The patent applies partial action by using the bootstrap capacitor only during the specific phase when the low side output transistor is ON. The capacitor charges during this period and then discharges to provide the high side gate drive, rather than continuously maintaining high voltage. This phased approach reduces overall delay while achieving the necessary voltage levels for high speed switching
2Reliability
If dead time is set longer to accommodate varying transmission delay times, then reliable transistor switching is ensured, but high speed switching becomes difficult
Solution Approach 1:
The patent implements dynamic dead time adjustment through the bootstrap capacitor mechanism. The dead time is automatically optimized based on the charging and discharging characteristics of the capacitor, which adapt to the actual circuit conditions. This dynamic approach reduces the need for excessive fixed dead time while maintaining reliable switching, thereby enabling higher switching frequencies
3Productivity
If detection transistors are connected in series with output transistors to detect turning off, then dead time can be contracted for high speed switching, but current flows during on-period causing power loss
Solution Approach 1:
The patent segments the detection function from the power handling path by using the bootstrap capacitor to isolate the detection circuitry from the main current path. The detection transistors monitor voltage levels through the capacitor coupling rather than carrying full load current, separating the detection function from power conduction to minimize power loss while maintaining high speed detection capability
4Ease of operation
If level shifter circuit is used to shift gate voltages, then high side transistor can be controlled, but current flows through the circuit causing power loss and potential malfunctions due to noise
Solution Approach 1:
The patent applies beforehand cushioning by using the bootstrap capacitor to pre-charge and isolate voltage levels before signal transmission. The capacitor acts as a cushioning element that absorbs voltage fluctuations and noise before they can propagate through the level shifter circuit, reducing power loss from unnecessary current flow while maintaining ease of gate voltage control
Data Source
AI summary
A driver circuit has a detector circuit including a high side detection transistor, a resistor, and a low side detection transistor connected to a high side output transistor and a low side output transistor. A clamping circuit converts a high voltage amplitude change signal generated at a connection point of the high side detection transistor and resistor to a signal clamped to a voltage range applied on the low side. An OR circuit outputs a signal taking the logical sum of an inverted control signal and an output of a low side first stage drive circuit. A level shifter circuit outputs a level-shifted signal of the OR circuit to a high side first stage drive circuit. A second OR circuit outputs a signal wherein the logical sum of an output signal of the clamping circuit and the control signal is inverted to the low side first stage drive circuit.