High-Side Driver Isolation Structure for Inductive Load Surge Protection
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Solution Overview
Problem
Power management integrated circuits (PMICs) face challenges in managing inductive loads, particularly due to negative voltage spikes that can cause high current surges, leading to transistor failure and latchup issues in high-side drivers when driving motors.
Innovation Solution
Incorporating an N-type isolation structure and a tracking and clamping circuit within high-side drivers, which provides low resistance during positive voltages and high resistance during negative spikes to block surge currents, along with an electrostatic discharge (ESD) protection circuit to manage voltage spikes between predetermined positive and negative thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-side drivers use conventional N-channel LDMOS transistors without isolation structures, then device complexity is reduced, but negative voltage spikes cause large surge currents that lead to transistor failure and latchup
Solution Approach 1:
An N-type isolation structure is introduced as an intermediary element between the P-type substrate and the N-channel LDMOS transistor. This isolation structure acts as a mediator that blocks surge currents from flowing into the substrate during negative voltage spikes, thereby protecting the transistor without requiring fundamental changes to the driver circuit architecture
Solution Approach 2:
The N-type isolation structure is pre-configured in the substrate before operation to provide protective cushioning against potential surge currents. This preventive measure is in place before any negative voltage spike occurs, cushioning the transistor against damage by blocking the surge current path in advance
2Reliability
If external diodes are added to each NFET to clamp negative voltage spikes, then transistor protection is improved, but device complexity and circuit footprint increase
Solution Approach 1:
The protection function previously requiring separate external diodes for each NFET is merged into a single integrated N-type isolation structure shared by all high-side drivers. This consolidation provides the same surge current blocking protection while reducing the overall circuit complexity and component count
Solution Approach 2:
The N-type isolation structure serves as a universal protection mechanism for all high-side drivers in the circuit, rather than requiring individual protection elements for each transistor. This multi-functional approach provides comprehensive protection across the entire driver stage through a single structural feature
3Reliability
If the N-type isolation structure is always connected to block surge currents, then transistor protection is improved, but normal operation is impaired due to blocked current flow during positive voltages
Solution Approach 1:
The electrical characteristics of the N-type isolation structure are made dynamic rather than static. The structure automatically adjusts its resistance based on the voltage polarity: presenting low resistance during positive voltages to allow normal current flow, and high resistance during negative spikes to block surge currents. This dynamic behavior maintains both protection and operational efficiency
Solution Approach 2:
The resistance parameter of the N-type isolation structure changes based on the applied voltage conditions. During normal positive voltage operation, the structure maintains low resistance to minimize impact on current flow. During negative voltage spikes, the resistance parameter transitions to high resistance to block surge currents, thereby adapting its electrical properties to operational conditions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents latchup and overstressing of high-side driver circuits by blocking surge currents during negative voltage spikes, ensuring reliable operation and extending the lifespan of the PMICs.
Implementation Method 1
provides low resistance during positive voltages and high resistance during negative spikes to block surge currents
Implementation Method 2
tracking and clamping circuit couples the N type isolation structure to the drain such that when a voltage on the third terminal is substantially positive that a voltage Viso on the isolation structure tracks the voltage Vd on the drain
Implementation Method 3
when the voltage on the third terminal spikes to a substantially negative voltage, that Viso is clamped to be no more negative than a predetermined negative voltage
Implementation Method 4
an electrostatic discharge (ESD) protection circuit to manage voltage spikes between predetermined positive and negative thresholds
Data Source
AI summary
A power management integrated circuit includes pairs of high-side and low-side drivers, sensing circuitry, and a processor. The high-side and low-side drivers are used in combination with external discrete NFETs to drive multiple windings of a motor. The N-channel LDMOS transistor of each high-side driver has an associated isolation structure and a tracking and clamping circuit. If the voltage on a terminal of the integrated circuit pulses negative during a switching of current flow to the motor, then the isolation structure and tracking and clamping circuit clamps the voltage on the isolation structure and blocks current flow from the substrate to the drain. An associated ESD protection circuit allows the voltage on the terminal to pulse negative. As a result, a large surge of current that would otherwise flow through the high-side driver is blocked, and is conducted outside the integrated circuit through a body diode of an external NFET.