Integrated High-Side Driver With Level Shifting for N-P LDMOS
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Solution Overview
Problem
Conventional bimodal N-P-LDMOS devices require two separate control signals and external components, leading to increased complexity, cost, and parasitic effects, which hinder their efficient integration and operation.
Innovation Solution
An integrated high-side driver is implemented on a single chip, incorporating an internal level shifter and P-LDMOS driver to convert low-voltage input signals to high-voltage control signals for the P-gate, reducing the need for external components and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate driver circuits are used for N-channel and P-channel MOSFETs, then each transistor can be optimized for its specific requirements, but the device complexity and area increase
Solution Approach 1:
The patent combines the driver circuits for N-channel and P-channel MOSFETs into a single integrated driver circuit. This driver circuit includes a first output stage for driving the N-channel MOSFET and a second output stage for driving the P-channel MOSFET, both integrated within the same device. The integration reduces the overall complexity and area while maintaining the ability to optimize each transistor's driving requirements through dedicated output stages.
Solution Approach 2:
The integrated driver circuit performs multiple functions by providing separate output stages for both N-channel and P-channel MOSFETs within a single circuit block. The driver circuit can independently control both types of transistors, enabling it to handle different voltage levels and current requirements for each transistor type while occupying a single device footprint.
2Stability of the object's composition
If high-side P-channel MOSFETs are used for high-side switching, then voltage matching is improved, but the speed of operation decreases compared to N-channel MOSFETs
Solution Approach 1:
The patent introduces an N-channel MOSFET as an intermediary device in the high-side switching path. The N-channel MOSFET operates in the linear region to provide a low-resistance path, enabling fast switching speeds. This N-channel MOSFET is controlled by the integrated driver circuit, which generates appropriate gate drive signals to ensure the N-channel MOSFET operates correctly as an intermediary between the control logic and the P-channel MOSFET load.
3Speed
If N-channel MOSFETs are used for high-side switching, then switching speed is improved, but voltage matching and level-shifting requirements increase complexity
Solution Approach 1:
The patent combines the level-shifting functionality into the integrated driver circuit that directly drives the N-channel MOSFET's gate. The driver circuit includes circuitry that automatically performs the necessary level shifting from the logic level to the appropriate gate drive voltage for the N-channel MOSFET, eliminating the need for external level-shifting components and reducing overall system complexity.
4Stability of the object's composition
If P-channel MOSFETs are used for low-side switching, then voltage matching is improved, but the speed of operation decreases
Solution Approach 1:
The patent inverts the conventional approach by using N-channel MOSFETs for low-side switching instead of P-channel MOSFETs. The N-channel MOSFET provides fast switching speeds in the low-side position where it can efficiently discharge the load current to ground. This configuration leverages the superior switching characteristics of N-channel MOSFETs while maintaining voltage matching through the integrated driver circuit's output stage design.
Data Source
Figure 1~2A
Figure 2B
Figure 2C~3
AI summary
In described examples, an integrated circuit chip (102) includes a bimodal power N-P -Laterally Diffused Metal Oxide Semiconductor (LDMOS) device (104) having an N-gate (GN) coupled to receive an input signal (IN) and a level shifter (108) coupled to receive the input signal and to provide a control signal to a P-gate driver (106) of the N-P-LDMOS device.