High-Side Driving Circuit Parasitic Capacitance Control
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Solution Overview
Problem
High-breakdown-voltage NMOS transistors in high-side driving circuits face issues with parasitic capacitance, leading to signal delays and abnormal operations due to non-negligible parasitic capacitance between drain, source, and gate, which affects the transmission of set and reset signals, resulting in incorrect switching states of high-side transistors.
Innovation Solution
A driving circuit with a level shift circuit, open drain circuit, latch circuit, and latch stabilization circuit is employed, where the latch stabilization circuit selects and fixes a node to a low level, reducing power consumption and enabling high-speed switching by canceling out parasitic capacitance effects through assist currents, ensuring precise control of high-side transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high-breakdown-voltage NMOS transistors are used in the level shift circuit, then the circuit can operate at high voltages, but parasitic capacitance between drain, source, and gate causes signal delays and abnormal operations
Solution Approach 1:
The patent introduces a latch circuit as an intermediary between the level shift circuit and the high-side transistor. This latch circuit captures and holds the set/reset signals, preventing parasitic capacitance effects from causing signal delays and abnormal operations. The latch circuit acts as a buffer that isolates the high-voltage switching node from the control signals, thereby maintaining signal transmission accuracy while enabling high-voltage operation.
Solution Approach 2:
The patent employs a bootstrap circuit that pre-charges the gate of the high-side transistor before the actual switching operation. By preliminarily establishing the necessary voltage conditions through the bootstrap capacitor, the circuit reduces the impact of parasitic capacitance during the switching transition, thereby preventing signal delays and ensuring reliable operation at high breakdown voltages.
2Speed
If assist currents are used to cancel parasitic capacitance effects, then switching speed improves, but power consumption increases
Solution Approach 1:
The patent uses periodic pulse signals to control the high-side transistor switching. By applying short-duration set and reset pulses only when needed for state transitions, the circuit achieves fast switching speed while minimizing power consumption. The latch circuit maintains the state between pulses without requiring continuous current, thereby resolving the contradiction between switching speed and power consumption.
Solution Approach 2:
The latch circuit is designed to maintain its state using the stored energy from the bootstrap capacitor and the inherent properties of the cross-coupled transistors. Once set or reset, the circuit sustains its state without requiring additional power, achieving fast switching when needed while consuming minimal power during state maintenance. This self-sustaining mechanism resolves the power-speed contradiction.
3Speed
If the latch circuit state is allowed to float during voltage transitions, then the circuit responds quickly to voltage changes, but the transistor switching state becomes incorrect
Solution Approach 1:
The latch circuit employs cross-coupled transistors that provide positive feedback to maintain a stable binary state. When a set or reset pulse is applied, the feedback mechanism quickly reinforces the state transition and prevents floating conditions during voltage transitions. This feedback ensures that the transistor switching state remains accurate and reliable while maintaining fast response to control signals.
Solution Approach 2:
The bootstrap circuit pre-charges the gate capacitor before switching operations, creating a voltage cushion that prevents the latch circuit from entering a floating state during transitions. This preliminary voltage preparation ensures that the latch circuit maintains a definite logic level throughout the switching process, thereby preventing incorrect transistor states while preserving fast response capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution dramatically reduces power consumption and ensures precise control of high-side transistors, maintaining correct switching states even under sudden voltage changes, thereby improving the reliability and efficiency of high-side transistor driving circuits.
Implementation Method 1
The bootstrap capacitor C1 is arranged between a bootstrap terminal (or bootstrap line) VB and the switching terminal VS. When the switching voltage VS is set to the low level (0 V), the capacitor C1 is charged via the rectifier element D1.
Implementation Method 2
A DC voltage VREG (which is higher than VGS(th)) is applied to the bootstrap terminal VB via the rectifier element D1.
Data Source
AI summary
A high-side driving circuit drives a high-side transistor configured as an N-channel or NPN transistor, according to an input signal. A level shift circuit level shifts the input signal. A latch stabilization circuit selects one node that corresponds to an output of the level shift circuit, from among a first node and a second node configured as complementary nodes provided to a latch circuit, and sinks a current from the node thus selected.