High-Side FET Gate Control With Two-Stage Bootstrap Charging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Switched mode power supplies (SMPS) face challenges with high-frequency ringing and efficiency reduction due to parasitic elements, particularly in high-side n-type FETs, which require large bootstrap capacitors and consume significant silicon area, leading to electromagnetic interference (EMI) and reduced reliability.
Innovation Solution
A two-stage turn-on process for high-side n-type FETs is implemented, where the gate terminal is first charged to the input voltage (VIN) and then further charged by a bootstrap capacitor, reducing the size of the bootstrap capacitor and minimizing parasitic charging, thus reducing ringing and EMI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large bootstrap capacitor is used to drive the high-side n-type FET, then the FET can be maintained in a conductive state, but the silicon area consumed increases and parasitic effects are exacerbated
Solution Approach 1:
The patent segments the capacitor into two functional parts: a first capacitor coupled to the gate terminal for primary charging, and a second capacitor coupled to the source terminal for bootstrap functionality. This segmentation allows each capacitor to be optimized independently, reducing the total silicon area while maintaining FET conduction reliability.
Solution Approach 2:
The patent introduces a switch as an intermediary element between the capacitors and the FET terminals. This switch enables dynamic reconfiguration of the capacitor connections, allowing the system to achieve proper FET gating with smaller capacitor values by strategically timing the charging paths.
2Reliability
If a large bootstrap capacitor is used, then the high-side FET remains conductive, but electromagnetic interference and ringing increase
Solution Approach 1:
By dividing the capacitor functionality between two smaller capacitors rather than using one large capacitor, the patent reduces the total parasitic inductance and capacitance. This segmentation minimizes the oscillatory effects and EMI generation while maintaining the necessary charge storage for FET conduction.
Solution Approach 2:
The patent changes the electrical parameters of the capacitive network by using two smaller capacitors with optimized values rather than one large capacitor. This parameter change reduces the time constants and resonant frequencies that cause ringing, while still providing sufficient charge for reliable FET operation.
3Speed
If the gate capacitance is charged directly from the power source, then charging speed is fast, but voltage spikes and parasitic effects occur
Solution Approach 1:
The patent implements preliminary action by first charging the first capacitor from the power source before using it to charge the FET gate. This staged approach allows the capacitor to be pre-charged at optimal conditions, then discharged in a controlled manner to the gate, avoiding direct connection spikes and parasitic effects.
Solution Approach 2:
The first capacitor acts as an intermediary energy storage element between the power source and the FET gate. It buffers the charging process, absorbing the power source voltage and releasing it in a controlled manner to the gate, thereby eliminating voltage spikes and reducing parasitic charging effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-stage turn-on process reduces the size of the bootstrap capacitor by approximately 20-25% and minimizes parasitic charging, leading to reduced electromagnetic interference and improved efficiency by maintaining the high-side FET in a conductive state while controlling parasitic effects.
Implementation Method 1
a capacitor having a first plate and a second plate, the first plate coupled to the driver output
Implementation Method 2
charging a gate capacitance of a transistor from the power source to pre-charge the transistor
Data Source
AI summary
In some examples, an apparatus includes a driver having a driver output, a capacitor having a first plate and a second plate, the first plate coupled to the driver output, and a transistor having a transistor gate, a transistor source, and a transistor drain. The apparatus also includes a first switch coupled between the second plate and the transistor gate, a second switch coupled between the second plate and the transistor drain, and a third switch coupled between the transistor gate and the transistor drain.