High-Side FET With Guard Ring for Voltage Tolerance
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Solution Overview
Problem
Conventional high-side MOSFETs suffer from limited voltage tolerance and electric field punching through, leading to performance issues in high-side switching configurations, which are exacerbated by the trend of miniaturization and the need for high performance.
Innovation Solution
A high-side field effect transistor design featuring a substrate with specific deep well and well regions, source and drain regions, gate structures, and a guard ring, optimized with varying doping concentrations and geometries to enhance voltage tolerance and prevent electric field punching through.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional high-side MOSFET structure is used, then the device can be manufactured with standard processes, but the voltage tolerance is limited and electric field punching through occurs
Solution Approach 1:
The substrate structure is segmented into multiple functional regions: a first deep well region for primary voltage blocking, a second deep well region for additional voltage tolerance, a first well region for field control, and second well regions for edge protection. This segmentation allows each region to address specific electric field management tasks, collectively achieving high voltage tolerance without requiring excessive complexity in any single region.
Solution Approach 2:
The patent implements a nested well structure where the first well region is disposed on the first deep well region, and the second well regions are disposed in the second deep well region. This nested arrangement creates concentric zones of doping that progressively manage the electric field from the surface to the substrate depth, enabling high voltage tolerance while maintaining a compact overall structure.
2Volume of moving object
If the MOSFET size is minimized to meet market trends, then manufacturing cost and integration are improved, but electric field punching through becomes more severe
Solution Approach 1:
The patent applies local quality by creating regions with different doping concentrations and types at specific locations. The guard ring structure with appropriately doped second well regions provides localized field control at the device periphery, while the deep well regions provide localized voltage blocking. This localized optimization allows miniaturization without sacrificing electric field control, as each region is tailored to its specific functional requirement.
Solution Approach 2:
The first and second well regions act as intermediary structures between the high-field drain region and the substrate. These intermediary regions with graded doping profiles smoothly transition the electric field, preventing direct punching through to the substrate. This mediator approach allows compact device design while maintaining reliable electric field control through the intermediate well structures.
3Reliability
If deep well regions are added to improve voltage tolerance, then high-side ability is enhanced, but manufacturing complexity increases
Solution Approach 1:
The deep well regions are formed as preliminary structures before the final device fabrication steps. By pre-defining the voltage blocking regions and field control zones in the substrate, subsequent processing steps can focus on forming the standard MOSFET structures. This preliminary action approach separates the complex voltage tolerance functionality from the standard device fabrication, making the overall manufacturing process more manageable despite the enhanced high-side ability.
Data Source
AI summary
The present invention provides a transistor comprising a substrate having a surface; a first deep well region in the substrate; a second deep well region in the substrate, isolated from and encircling the first deep well region; a first well region in the substrate and on the first deep well region; two second well regions in the second deep well region and respectively at two opposite sides of the first well region; a source region in the first well region and adjacent to the surface; two drain regions in the two second well regions respectively and adjacent to the surface; two gate structures on the surface, wherein each of the two gate structures is between the source region and one of the drain regions respectively; and a guard ring in the substrate encircling the second deep well region, and on the periphery of the transistor.