Dual-Mode High-Side FET Driver for Phase-Node Slew Control

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Solution Overview

Problem

The existing dual-mode high-side power field-effect transistor (FET) driving techniques for power regulators face issues with slew rate variations at the phase node, leading to increased power loss, reliability concerns, and malfunction of sensitive components due to rapid current surges and ringing, which are not adequately addressed by current control modes.

Innovation Solution

The implementation of a dual-mode high-side FET driving technique that switches the high-side FET between constant-current and constant-voltage modes based on the phase node voltage threshold, using a driver circuit and controller to manage the slew rate and prevent voltage overshoot, thereby controlling currents and reducing power loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the high-side FET is switched on rapidly to improve power conversion speed, then the productivity is improved, but the slew rate variations cause increased power loss and reliability concerns

Engineering Contradiction:
Improvepower conversion speedVSAvoidpower loss
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The driver circuit dynamically switches between constant-current mode and constant-voltage mode based on the real-time voltage level at the phase node. During the rising edge when voltage is below threshold, constant-current mode limits the slew rate to prevent excessive power loss. When voltage exceeds threshold, constant-voltage mode enables faster switching. This dynamic adaptation resolves the contradiction between fast switching and power loss reduction.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the operating parameters of the high-side FET driver by selectively switching between two distinct control modes (constant-current and constant-voltage) based on the phase node voltage threshold. This parameter change allows the system to optimize the trade-off between switching speed and power loss at different operating points during the FET switching cycle.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the high-side FET switching speed is increased to improve power conversion efficiency, then the productivity is improved, but current surges and ringing occur causing reliability concerns

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoidreliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The driver circuit applies preliminary anti-action by enabling constant-current mode before the phase node voltage reaches the threshold level during the switching transition. This pre-limiting of the slew rate prevents the formation of excessive current surges and ringing that would otherwise occur during rapid FET switching, thereby protecting the system reliability while still maintaining efficient power conversion.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The constant-current control mode acts as a cushioning mechanism during the critical rising edge of the phase node voltage. By limiting the rate of voltage change before the voltage reaches the threshold, the system cushions against the harmful effects of rapid switching such as current surges and oscillations, ensuring reliable operation during high-efficiency power conversion.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If constant-voltage mode is used throughout the switching cycle to maximize switching speed, then the productivity is improved, but voltage overshoot occurs leading to malfunction of sensitive components

Engineering Contradiction:
Improveswitching speedVSAvoidvoltage overshoot
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The switching cycle is segmented into two distinct phases based on the phase node voltage threshold: a first phase where constant-current mode is applied to prevent voltage overshoot, and a second phase where constant-voltage mode is applied to maximize switching speed. This temporal segmentation allows the system to avoid harmful voltage overshoot while still achieving fast switching, by applying the appropriate control mode at the appropriate time during the switching transition.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12057765B2Dual-mode high-side power field-effect transistor driver for power regulators
Publication Date: 2024.08.06 RENESAS ELECTRONICS AMERICA INC
  • US12057765B2 patent drawing
  • US12057765B2 patent drawing
  • US12057765B2 patent drawing

AI summary

Apparatuses and methods for operating a power converter are described. An integrated circuit can be integrated in a high-side driver of a high-side fiend-effect transistor (FET) of the power converter. The integrated circuit can detect a phase node voltage of a power integrated circuit. The integrated circuit can, in response to the phase node voltage being less than a threshold voltage, operate a high-side FET of the power integrated circuit in a constant-current mode. The integrated circuit can, in response to the phase node voltage being greater than the threshold voltage, operate the high-side FET of the power integrated circuit in a constant-voltage mode.