High-Side FET Adaptive Turn-Off for Voltage Spike Suppression

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Solution Overview

Problem

Conventional switching voltage regulators experience high drain-to-source voltage spikes during the turn-off of high-side FETs, leading to potential damage and increased silicon area requirements due to large pull-up devices or fixed timing delays that introduce variability and power loss.

Innovation Solution

A circuit design that weakens the pull-down strength of the high-side FET by turning off a pull-down transistor when the switch node reaches a certain voltage, reducing voltage ringing and avoiding the need for large pull-up devices or fixed timing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If large pull-up devices are used to reduce drain-to-source voltage spikes, then the high-side FET is protected from damage, but the silicon area increases

Engineering Contradiction:

Improveprotection from voltage spikesVSAvoidsilicon area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The pull-up function is segmented into two stages: a strong pull-up device (first pull-down FET) that operates only during the critical turn-off transient, and a weaker pull-up device (second pull-down FET) that operates during steady state. This segmentation allows the strong protection capability when needed while minimizing the continuous silicon area requirement.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The pull-up strength is made dynamic by using a controller to selectively enable or disable the first pull-down FET based on the operating state. During high-side FET turn-off, the first pull-down FET is enabled to provide strong voltage spike suppression. During steady state, it is disabled to reduce power consumption and silicon area utilization.

Inventive Principle:

Principle #15Dynamics

2Reliability

If fixed timing delays are used to control turn-off, then the voltage spikes are managed, but power loss increases and variability is introduced

Engineering Contradiction:

Improvevoltage spike managementVSAvoidpower loss

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The controller monitors the voltage at the source of the high-side FET and uses this feedback to dynamically control the pull-down FETs. When the source voltage drops below a threshold during turn-off, the controller activates the first pull-down FET to suppress voltage spikes. This feedback mechanism replaces fixed timing delays with adaptive control, reducing power loss and eliminating timing variability.

Inventive Principle:

Principle #23Feedback

3Stability of the object's composition

If pull-down transistors remain continuously active, then voltage ringing is suppressed, but power consumption increases

Engineering Contradiction:

Improvevoltage stabilityVSAvoidpower consumption

Core Design Contradiction:

Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The pull-down transistors operate periodically rather than continuously. The first pull-down FET is activated only during the brief turn-off transient when voltage spikes occur, and the second pull-down FET operates only when needed for steady-state voltage regulation. This periodic operation maintains voltage stability while dramatically reducing power consumption compared to continuous operation.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS20250373240A1High-side FET two-stage adaptive turn-off

Publication Date: 2025.12.04 TEXAS INSTRUMENTS INC

AI summary

In an example, a method includes providing a signal to a driver for a switching voltage regulator to turn off a high-side field effect transistor (FET) of the switching voltage regulator. The method also includes reducing a voltage at a source of the high-side FET. The method includes responsive to the signal, turning off a pull-down FET coupled to a gate of the high-side FET. The method also includes commutating current from the high-side FET to a low-side FET.