Configurable High-Side NMOS Gate Control Circuit
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Solution Overview
Problem
Existing gate driver circuits for high side n-channel MOSFETs face challenges in regulating the gate-to-source voltage (VGS) effectively, as they are either limited by the minimum breakdown voltage of Zener diodes or require high drive current, leading to inefficiencies and variability due to process and temperature variations.
Innovation Solution
A configurable gate control circuit that uses a charge pump, oscillator, comparator, and Schmitt trigger to regulate the gate-to-source voltage by adjusting the current through a series resistor, allowing for precise control of VGS independent of threshold voltages and leakage currents, using matched transistors and resistors to minimize process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Zener diodes are used to regulate gate-to-source voltage, then voltage regulation is achieved, but the regulation is limited by minimum breakdown voltage and suffers from process and temperature variations
Solution Approach 1:
The patent replaces the Zener diode breakdown mechanism with a charge pump voltage generation mechanism controlled by an oscillator and comparator. The charge pump generates a controlled current that flows through a series resistor to create a stable voltage drop, eliminating dependence on Zener breakdown voltage which is limited by minimum voltage requirements and process variations.
Solution Approach 2:
The patent changes the regulation mechanism from relying on fixed Zener breakdown voltage to using a dynamically controllable charge pump current. By adjusting the oscillator frequency and comparator threshold, the gate-to-source voltage can be precisely regulated without being constrained by minimum breakdown voltage or affected by temperature and process variations.
2Speed
If high drive current is used to charge the gate, then the MOSFET turns on faster, but power consumption increases
Solution Approach 1:
The patent uses an oscillator to generate periodic clock signals that drive the charge pump in pulsed mode. The charge pump delivers current in controlled pulses to charge the MOSFET gate, rather than requiring continuous high current. This periodic charging action achieves fast switching while significantly reducing average power consumption compared to continuous high-current drive approaches.
Solution Approach 2:
The patent employs a comparator that monitors the gate-to-source voltage and provides feedback control to the charge pump. When the voltage reaches the desired threshold, the comparator stops the charge pump operation, preventing excessive current flow and power consumption. This feedback mechanism ensures the MOSFET switches quickly when needed while minimizing power consumption during voltage regulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides reliable and accurate regulation of the gate-to-source voltage, reducing power consumption and variability, enabling efficient operation of high side n-channel MOSFETs by dynamically adjusting the gate voltage to any desired level, thus enhancing the reliability and efficiency of the gate driver circuit.
Implementation Method 1
A charge pump has: an output node coupled to the gate terminal; and a clock input
Implementation Method 2
An oscillator is coupled to generate a clock signal
Implementation Method 3
A comparator is coupled to output the enable signal in response to a comparison between a reference current and a current through a series resistor
Implementation Method 4
The series resistor is coupled to the gate terminal
Data Source
AI summary
In described examples, a transistor has: a source and a drain coupled between a supply voltage and an output terminal; and a gate terminal. A charge pump has: an output node coupled to the gate terminal; and a clock input. An oscillator is coupled to generate a clock signal. A clock enable circuit is coupled to: receive the clock signal; and selectively output the clock signal to the clock input, responsive to an enable signal. A comparator is coupled to output the enable signal in response to a comparison between a reference current and a current through a series resistor. The series resistor is coupled to the gate terminal.