High-Side NMOS Gate Drive Circuit for Low Standby Loss
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing drive circuits for high-side load switches in power converters face challenges in efficiency, operational speed, and reliability due to sensitivity to circuit parasitics and high standby power losses.
Innovation Solution
A drive circuit comprising a signal conversion circuit, a signal buffer circuit, and a drive circuit is used to control high-side high voltage NMOS switches, which includes a signal conversion circuit to generate a high-side signal, a signal buffer circuit to generate a buffered signal, and a drive circuit to generate a gate drive signal, thereby controlling the conductivity state of the NMOS switch, with a power supply to power the signal and drive circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If existing drive circuits are used for high-side load switches, then the circuit can operate, but it suffers from high standby power losses and sensitivity to circuit parasitics
Solution Approach 1:
The drive circuit is segmented into multiple functional blocks: a signal conversion circuit (104) that converts low-side signals to high-side signals, a signal buffer circuit (108) that buffers the converted signals, and a drive buffer circuit (112) that provides the final drive signal to the NMOS switch. This segmentation allows each circuit block to be optimized for its specific function, reducing overall standby power loss and minimizing sensitivity to parasitic effects in any single section.
Solution Approach 2:
The patent introduces intermediate signal processing stages between the control signal and the final switch drive. The signal conversion circuit acts as an intermediary to generate appropriate high-side signals, while the buffer circuits serve as intermediaries to isolate and protect against parasitic effects. This multi-stage intermediary approach reduces direct exposure to parasitic elements and lowers standby power consumption compared to direct drive circuits.
2Reliability
If the drive circuit includes multiple circuit blocks for signal conversion and buffering, then efficiency and reliability improve, but device complexity increases
Solution Approach 1:
While segmentation into multiple blocks improves reliability, the patent implements each block using standard, well-understood circuit topologies. The signal conversion circuit uses conventional voltage level shifting techniques, and the buffer circuits employ standard CMOS buffer designs. This approach maintains relative simplicity within each segment while achieving high overall reliability through the modular architecture.
Solution Approach 2:
The buffer circuits are designed to perform multiple functions: signal buffering, impedance matching, and protection against parasitic effects. This multi-functionality reduces the need for additional dedicated circuits, thereby limiting the increase in overall device complexity while still improving reliability through enhanced signal integrity and parasitic immunity.
3Use of energy by moving object
If the drive circuit is optimized for high voltage NMOS switches, then power converter efficiency improves, but the circuit requires multiple specialized components
Solution Approach 1:
The signal conversion circuit is specifically designed to generate high-side signals with voltage levels and timing characteristics optimized for high voltage NMOS switches. By changing the voltage parameters and signal timing in the conversion stage, the circuit achieves high power converter efficiency. The buffer circuits then maintain these optimized parameters while providing the necessary drive current, reducing the need for additional specialized components elsewhere in the system.
Data Source
AI summary
A circuit. The circuit includes a switch having a gate terminal, a source terminal and a drain terminal, a switch driver circuit connected to the gate terminal and arranged to control an on-state and an off-state of the switch, the switch drive circuit including: a signal conversion circuit arranged to receive a control signal and in response generate a high-side signal; a signal buffer circuit coupled to the signal conversion circuit and arranged to receive the high-side signal and in response generate a buffered signal; and a drive circuit coupled to the signal buffer circuit and arranged to receive the buffered signal and in response generate a gate drive signal that causes the switch to transition between the on-state and the off-state. In one aspect, the switch is an NMOS transistor having a gate, a source and a drain, where the source and drain are at substantially high voltage.