High-Side Transistor Partitioning for Faster Low-Loss Switching
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Solution Overview
Problem
In switch-mode power supplies, the power transistor's control terminal capacitance requires significant current to charge or discharge, leading to reduced efficiency due to increased overlap switching losses and limited slew rate of the voltage across the high-side transistor.
Innovation Solution
The high-side transistor is partitioned into two switches, each with reduced gate-to-drain capacitance, and the driver circuit is designed to provide a strong pull-up for the first switch and a weaker pull-up for the second switch, with a delay circuit ensuring the second switch is closed only after the first switch and a predetermined voltage condition are met.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a single power transistor is used to handle high current, then the current handling capability is sufficient, but the gate-to-drain capacitance is large requiring significant charging current and causing high overlap switching losses
Solution Approach 1:
The power transistor is divided into multiple parallel transistor cells (e.g., 8 cells) that can be independently controlled. By partitioning the transistor array into separate switch groups (first switch and second switch), the gate-to-drain capacitance of each group is reduced compared to controlling the entire array simultaneously. This segmentation allows the driver circuit to charge smaller capacitance values, reducing the transient current requirement and overlap switching losses.
2Speed
If the driver circuit provides strong pull-up to charge gate-to-drain capacitance quickly, then the switching speed is improved, but the transient current demand increases causing voltage droop and reduced efficiency
Solution Approach 1:
By dividing the transistor array into multiple switch groups with separate control, the total gate-to-drain capacitance is effectively divided. Each driver circuit only needs to charge a portion of the total capacitance, reducing the transient current demand while maintaining fast switching speed. The first driver charges the first switch group's capacitance, and the second driver charges the second switch group's capacitance, avoiding the need for a single high-current pulse.
Solution Approach 2:
The driver circuit is designed to provide strong pull-up capability specifically for the first switch group, which is activated first. This preliminary action of charging the first group's capacitance with strong pull-up enables fast initial switching, followed by the second switch group activation. This staged approach allows optimized current distribution rather than simultaneous high-current demand across all cells.
3Power
If multiple transistor cells are controlled simultaneously, then the current handling is optimized, but the gate driver must supply high current to charge the total capacitance quickly
Solution Approach 1:
The transistor array is segmented into multiple switch groups (first switch and second switch), each controlled by separate driver circuits. This segmentation maintains the total current handling capability by keeping all transistor cells in parallel, but reduces the gate driver current consumption by dividing the capacitance charging task. Each driver handles only its assigned group's capacitance, significantly reducing individual and total driver current requirements compared to simultaneous control of all cells.
Data Source
AI summary
A circuit includes a transistor, a first driver, a second driver, and a delay circuit. The transistor includes an array of transistor cells partitioned into a first switch and a second switch. The first driver is configured to control the first switch. The second driver is configured to control the second switch. The delay circuit is coupled between the first driver and the second driver. The delay circuit is configured to delay closure of the second switch until the first switch is closed and a voltage across the first switch is less than a predetermined voltage.