High-Side Voltage Sampling With Capacitive Clock Shifters
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Solution Overview
Problem
Existing methods for measuring high-side voltages in battery systems, such as voltage dividers and voltage-to-current converters, suffer from power consumption, large silicon area occupation, reduced signal-to-noise ratio, and gain errors, and require high power supplies, making them inefficient and inaccurate.
Innovation Solution
A capacitive coupled clock shifter and reset circuit system is employed to level-shift clock signals to appropriate voltage ranges, ensuring accurate measurement without additional power consumption or errors, using capacitive coupled clock shifters and reset circuits to control sampling switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage divider is employed to convert high voltage to low voltage range, then the voltage measurement circuit is protected from damage, but extra power consumption is caused and large silicon area is occupied
Solution Approach 1:
The patent extracts the voltage division function from the measurement circuit by using the inherent high-impedance nodes of the capacitive coupled clock shifter, eliminating the need for a separate voltage divider circuit. This removes the power-consuming and area-occupying component while maintaining circuit protection.
Solution Approach 2:
The capacitive coupled clock shifter is designed to perform multiple functions: clock signal shifting, voltage level adaptation, and implicit voltage division for measurement. By making this component multi-functional, the patent eliminates dedicated voltage division hardware, reducing power consumption and silicon area.
2Reliability
If a voltage divider is employed to convert high voltage to low voltage range, then the voltage measurement circuit is protected from damage, but the signal-to-noise ratio is reduced
Solution Approach 1:
The patent removes the voltage divider that degrades signal-to-noise ratio and instead uses the high-impedance nodes naturally present in the capacitive coupled clock shifter architecture, which do not introduce additional noise while providing the necessary voltage level adaptation.
3Reliability
If a voltage divider is employed to convert high voltage to low voltage range, then the voltage measurement circuit is protected from damage, but gain errors and offsets are introduced due to resistor mismatch
Solution Approach 1:
The patent extracts the voltage division functionality from a separate resistor-based voltage divider and integrates it into the capacitive coupled clock shifter's inherent high-impedance nodes, eliminating resistor mismatch errors while maintaining circuit protection through the same measurement nodes.
4Measurement precision
If a voltage-to-current converter is used to measure high voltage signal, then the high side voltage is converted to current flowing through a small resistor, but a high power supply is required which causes the same issues as voltage divider
Solution Approach 1:
The patent replaces the voltage-to-current converter approach (which requires high power supply) with a direct capacitive sampling method that uses voltage division through high-impedance nodes, eliminating the need for power-consuming current conversion circuitry while maintaining measurement accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system accurately measures high-side voltages without extra power consumption or introduction of errors, providing reliable and efficient voltage sampling for battery systems.
Implementation Method 1
a first capacitive coupled clock shifter configured to level-shift a first clock signal to obtain a first gate drive signal
Data Source
AI summary
An apparatus includes a first sampling switch coupled between a first voltage bus and a sampling capacitor, a first clock generator configured to produce a first gate drive signal fed into a gate of the first sampling switch, the first clock generator comprising a first capacitive coupled clock shifter, a first reset circuit and a second reset circuit, a second sampling switch coupled between a second voltage bus and the sampling capacitor, and a second clock generator configured to produce a second gate drive signal fed into a gate of the second sampling switch, the second clock generator comprising a second capacitive coupled clock shifter, a third reset circuit and a fourth reset circuit.