High-Speed DAC Switching With Positive Feedback for Low Distortion

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Solution Overview

Problem

High-speed digital-to-analog converters (DACs) face challenges with distortion and increased power consumption at high frequencies, leading to code-dependent glitching and higher power consumption that increases linearly with clock frequency.

Innovation Solution

The implementation of a DAC with switch drivers and output switches that include positive feedback circuitry to address floating node issues, reduce latency, and operate in current steering modes with bi-polar quad or hex switching schemes, along with dual- or tri-level decoding formats to manage current flow effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-speed DACs operate at high clock frequencies, then conversion speed is improved, but power consumption increases linearly with clock frequency

Engineering Contradiction:
Improveconversion speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent employs periodic clocked switching actions where switches are activated only during specific clock phases rather than continuously. The switch driver uses clock signals to periodically control the switching of current sources, reducing average power consumption while maintaining high-speed conversion capability through efficient use of switching cycles.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements dynamic switching schemes where the DAC operates in different modes (single-ended or differential) based on input conditions. The switch driver dynamically controls current steering based on digital input codes, allowing the circuit to adapt its power consumption and performance characteristics to match the actual conversion requirements rather than operating at maximum power continuously.

Inventive Principle:
Principle #15Dynamics

2Speed

If high-speed DACs operate at high clock frequencies, then conversion speed is improved, but distortion increases due to code-dependent glitching

Engineering Contradiction:
Improveconversion speedVSAvoidoutput linearity
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent implements feedback mechanisms through differential switching schemes where the output is controlled to minimize glitches. The switch driver uses feedback from the digital input codes to control the switching timing and sequence, ensuring that current transitions are synchronized and balanced, thereby reducing code-dependent glitching and improving output linearity at high speeds.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent employs asymmetric switching schemes where different switching sequences are applied for different current sources based on the digital input code. By asymmetrically controlling the switching of individual current sources in a current-steering DAC, the patent balances the total current transitions and reduces glitching artifacts while maintaining high conversion speed.

Inventive Principle:
Principle #4Asymmetry

3Reliability

If positive feedback circuitry is added to switch drivers, then floating node issues are resolved and latency is reduced, but device complexity increases

Engineering Contradiction:
Improvefloating node controlVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces positive feedback circuitry in the switch driver to resolve floating node issues that occur during switching transitions. The feedback connections provide defined voltage paths during critical switching moments, ensuring stable node voltages and reducing uncertainty in the switching behavior. This feedback mechanism is integrated into the existing switch driver architecture with minimal additional components.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent implements preliminary action by pre-charging or pre-discharging certain nodes before the main switching event occurs. The positive feedback circuitry is configured to act in advance of the primary switching transition, preparing the voltage states of critical nodes to prevent floating conditions. This preliminary action reduces latency by eliminating the need for slow discharge paths during switching transitions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3644514B1High-speed digital-to-analog converter
Publication Date: 2024.03.13 MEDIATEK SINGAPORE PTE LTD
  • EP3644514B1 patent drawingFigure 1
  • EP3644514B1 patent drawingFigure 2
  • EP3644514B1 patent drawingFigure 3A

AI summary

A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.