High-Speed DAC Switching for Low-Glitch RF Linearity
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Solution Overview
Problem
High-speed digital-to-analog converters (DACs) face challenges with increased distortion and power consumption at higher frequencies, particularly due to code-dependent glitching, which affects their performance in applications like delta-sigma analog-to-digital converters.
Innovation Solution
The implementation of a high-speed DAC design that includes switch drivers with positive feedback circuitry and dual or tri-level switching schemes, which address floating node issues and reduce latency by forcing latches to make rapid decisions, and integrate XOR gates to enhance data independence and reduce noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed DAC operation is implemented, then conversion speed is improved, but distortion increases due to code-dependent glitching
Solution Approach 1:
The patent segments the switching operation into two distinct phases: a first switching operation for initial code transition and a second switching operation for subsequent code transitions. This segmentation allows the circuit to handle different switching scenarios separately, reducing code-dependent glitching while maintaining high-speed operation. The dual switching mechanism ensures that floating nodes are properly managed without compromising conversion speed.
Solution Approach 2:
The patent implements preliminary action by pre-charging or pre-discharging floating nodes before the actual switching event. This preparatory action ensures that nodes are in a known state before switching, preventing unpredictable glitching behavior. The circuit proactively manages node states to avoid distortion during high-speed conversions.
2Productivity
If high-speed switching is used to improve conversion rate, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic switching operations with controlled duty cycles. By alternating between different switching states and allowing periods of reduced activity, the circuit maintains high average conversion rates while reducing instantaneous power consumption. The periodic management of switching events prevents continuous high-power operation.
Solution Approach 2:
The patent implements dynamic switching strategies where the switching frequency and amplitude are adjusted based on the input signal characteristics. This dynamic adaptation allows the DAC to operate at high speeds when necessary while consuming less power during low-activity periods. The circuit dynamically manages its operational state to balance speed and power consumption.
Data Source
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AI summary
A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.