High Speed Data Path Testing via Coherent Clock Patterns
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Testing high-speed data channels, such as those in HDMI devices, is impractical due to the high power consumption and unfeasibility of generating high-speed bit clocks required for at-speed testing.
Innovation Solution
The method involves selecting a high-speed data path and driving coherent clock data patterns on remaining data paths using a low-speed base clock, allowing for sampling and testing without generating high-speed bit clocks, utilizing pattern generators and deserializers to emulate high-speed clocks with altered frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-speed bit clocks are generated for at-speed testing of data channels, then testing accuracy and reliability are improved, but power consumption increases and the complexity of clock generation becomes unfeasible
Solution Approach 1:
The patent uses data patterns on other data paths to copy the timing characteristics of the high-speed bit clock. Instead of generating an actual high-speed clock signal, coherent clock data patterns are driven on remaining data paths to emulate the clock's timing behavior, allowing the target data path to be tested at high speed without requiring a physical high-speed clock generator
Solution Approach 2:
The patent introduces coherent clock data patterns as an intermediary mechanism. These patterns serve as a mediator between the low-speed base clock and the high-speed data path under test, transferring timing information without requiring direct high-speed clock generation. The pattern generator and deserializer act as intermediaries to convert between low-speed control signals and high-speed test operations
2Measurement precision
If high-speed bit clocks are generated for at-speed testing, then testing precision is improved, but device complexity and feasibility deteriorate
Solution Approach 1:
The timing characteristics of the high-speed bit clock are copied through data patterns rather than being physically generated. Coherent clock data patterns on other data paths replicate the clock's timing behavior, enabling precise high-speed testing without the complexity of high-speed clock generation circuitry
Solution Approach 2:
The remaining data paths serve multiple functions: they carry normal data traffic and simultaneously generate coherent clock data patterns for testing the target data path. This multi-functionality eliminates the need for dedicated high-speed clock generation hardware, reducing overall device complexity while maintaining testing precision
3Productivity
If multiple data paths are tested simultaneously using traditional methods, then productivity is improved, but power consumption and complexity increase significantly
Solution Approach 1:
The patent merges the clock generation function with data transmission on remaining data paths. By combining normal data traffic with coherent clock pattern generation, the system enables simultaneous testing of multiple data paths without requiring separate high-speed clock generators for each path, thus improving productivity while controlling power consumption
Solution Approach 2:
Each data path under test uses the other data paths to provide its own high-speed timing reference. The system is self-sufficient, using its own internal data paths to generate the necessary timing signals for testing, eliminating the need for external high-speed clock sources and reducing overall power consumption
Data Source
AI summary
System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.