High-Speed Deserializer Circuitry for Precise Event Timing
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Solution Overview
Problem
Current techniques for detecting event timing are limited by their reliance on slower clock speeds and require calibration, offering limited precision and accuracy in measuring time intervals.
Innovation Solution
The use of high-speed deserializer circuitry to sample event occurrence signals and generate multi-bit parallel data, allowing for precise timestamp generation based on the bit period of the deserializer's operation rather than slower reference clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional counter-based timestamping is used, then the system is simple to implement, but the timing resolution is limited to several nanoseconds due to counter operating frequency
Solution Approach 1:
The patent changes the fundamental parameter of measurement frequency by using the high-speed deserializer's bit clock (operating at gigabit rates) instead of conventional counter clocks (operating at megahertz rates). This parameter change enables timing resolution in the picosecond range rather than nanosecond range, directly resolving the contradiction between measurement precision and device complexity.
Solution Approach 2:
The patent replaces the mechanical/electronic counter-based timing system with a digital signal processing approach using high-speed deserializers. Instead of relying on physical counter incrementing at limited frequencies, the system uses digital sampling and bit-period measurement, substituting the mechanical timing mechanism with a faster electronic/digital method.
2Measurement precision
If analog time interval measurement circuits are used, then short time intervals can be measured, but annual calibration is required to maintain accuracy
Solution Approach 1:
The high-speed deserializer-based timing system is self-calibrating because it uses its own internal bit clock and bit period as the reference for measurement. The system measures time intervals in units of its own operating bit periods, eliminating the need for external calibration references. The deserializer's internal timing mechanism serves itself, requiring no annual calibration to NIST standards.
Solution Approach 2:
The patent replaces the analog capacitor-charging measurement circuit with a digital counting method based on deserializer bit periods. Instead of measuring voltage changes from capacitor charging (which drifts and requires calibration), the system counts high-speed clock cycles from the deserializer's internal oscillator, providing inherent stability and eliminating calibration requirements.
3Measurement precision
If propagation delay techniques are used to subdivide measurement intervals, then sub-nanosecond resolution can be achieved, but the system becomes cumbersome as the number of sub-intervals grows and requires calibration
Solution Approach 1:
The patent replaces the complex propagation delay chain (requiring multiple gates and wires with different known delays) with a uniform high-speed clock counting method. Instead of using different physical paths with different delays, the system uses a single high-frequency clock source and counts cycles, dramatically simplifying the circuit while maintaining or improving resolution.
Solution Approach 2:
The patent changes the approach to interval subdivision by increasing the clock frequency parameter rather than adding more physical subdivision stages. Instead of dividing a slow clock into many slow intervals using propagation delays, the system uses a single fast clock whose natural period provides the fine resolution, eliminating the need for multiple subdivision stages.
Data Source
AI summary
Systems and methods are disclosed for precise event time measurement using high-speed deserializer circuitry. The described embodiments utilize high speed deserializer circuitry to achieve a precision based upon a bit period associated with the operation of the high speed operation of the deserializer circuitry rather than upon slower speed clock periods associated with reference clock signals. In certain embodiments, the disclosed systems and methods receive an event occurrence signal and use deserializer circuitry to sample the event occurrence signal and to produce multi-bit parallel data representing the event occurrence signal. Precise timestamps can then be generated based upon the multi-bit parallel data. Advantageously, the precision of these time measurements is associated with the bit period of the high speed operation of the deserializer circuitry and are not limited to lower speeds at which other circuitry within the system may be operating, for example, based upon a slower reference clock signal.