High-Speed DFE Circuit With Partial Regeneration and Low Loop Latency
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Solution Overview
Problem
Conventional decision-feedback equalization (DFE) systems face challenges in high-speed data transmission due to power and area consumption, loop latency, and critical path delay, especially at high data rates, which limits their ability to effectively cancel inter-symbol interference (ISI) while maintaining low power dissipation.
Innovation Solution
The implementation of a DFE system with a first stage using a pre-charging sense amplifier and a second stage regenerating amplifier, where the feedback signal is used to charge output nodes and apply regenerative gain, allowing for partial regeneration and resolution into non-return to zero (NRZ) digital values, thereby reducing RC time constant and loop latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-tap DFE is used to cancel ISI effectively, then equalization performance is improved, but power consumption and chip area increase significantly
Solution Approach 1:
The patent divides the feedback path into multiple taps, where each tap processes a previous symbol decision. This segmentation allows the system to cancel ISI from multiple previous symbols while using efficient circuit structures for each tap, reducing the overall power consumption compared to a single complex filter while maintaining effective equalization performance.
Solution Approach 2:
The patent applies different circuit optimizations to different parts of the DFE structure. Specifically, the feedback taps use optimized latch and adder circuits that are tailored for their specific function of canceling ISI from previous symbols, rather than using a uniform high-power design throughout the entire equalizer.
2Reliability
If larger number of tap weights are used to improve ISI cancellation, then equalization effectiveness is improved, but device complexity and area increase
Solution Approach 1:
The feedback equalizer is segmented into multiple independent taps, each handling a specific previous symbol. This segmentation allows the complex task of multi-symbol ISI cancellation to be divided into simpler, parallel operations, reducing the complexity of individual circuit blocks while achieving the overall equalization goal.
Solution Approach 2:
The patent implements a practical number of feedback taps that provides sufficient ISI cancellation for the given channel conditions, rather than implementing an excessively large number of taps that would unnecessarily increase complexity. This partial action approach achieves the necessary equalization performance with optimized circuit complexity.
3Speed
If full rate DFE architecture is used to process data at data rate frequency, then equalization speed is improved, but clock generation and distribution power consumption increases
Solution Approach 1:
The patent employs a fractional-delay structure where the feedback taps operate at a fraction of the data rate frequency. This periodic action allows the equalizer to process data at the full data rate while the clocking infrastructure operates at a lower, more power-efficient frequency, reducing the power consumption of clock generation and distribution.
4Use of energy by moving object
If de-multiplexing front-end is used to reduce clock frequency requirements, then power consumption is reduced, but loop latency increases
Solution Approach 1:
The patent incorporates a pre-charging mechanism that prepares the feedback path in advance before the actual data processing occurs. This preliminary action reduces the effective loop latency by pre-positioning the necessary feedback signals, allowing the de-multiplexed architecture to maintain low latency while operating at reduced clock frequencies for power efficiency.
Data Source
AI summary
An electronic-system for implementing decision-feedback equalization (DFE) includes a first stage including a first-amplifier. The first amplifier including an in-built adder circuit. The first amplifier being configured to charge one or more output nodes of the first amplifier to a first voltage using a summed signal based on input data and a feedback signal in response to a first-clock variation, wherein the feedback signal is a partially-regenerated analog output from a regenerating amplifier. A second stage is includes a second amplifier configured as the regenerating amplifier and connected to the one or more output nodes of the first amplifier, the second amplifier configured to amplify charged output nodes of the second stage to a second voltage in response to a second-clock variation and apply a regenerative gain to the amplified second-voltage during the second-clock variation to generate the partially-regenerated analog output. A third stage includes a slave latch that is configured to resolve the partially-regenerated analog output at the output nodes of the second stage into non-return to zero (NRZ) digital values at an output of the third stage.