High-Speed Divider Alignment Without Domain-Wide Clock Reset
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Solution Overview
Problem
Conventional high-speed clock distribution systems, such as those following JESD204B/C standards, require resetting and resynchronizing all clocks in a domain for dynamic phase adjustment of one device clock, leading to reduced system performance and efficiency due to additional circuit overhead and speed loss.
Innovation Solution
A timing alignment circuit that uses detection and control circuitry to align output signals of multiple dividers without resetting them, by comparing phases and adjusting divide ratios to synchronize specific edges of output signals, allowing dividers to operate at their final ratios without interruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If dynamic phase adjustment is performed on one device clock in conventional systems, then phase alignment is achieved, but all other clocks in the domain must be reset and resynchronized, reducing system performance and efficiency
Solution Approach 1:
The patent segments the clock domain into independent divider units, each with its own phase detection and control circuitry. This allows individual phase adjustment of specific dividers without affecting others, eliminating the need for system-wide resets while maintaining precise phase alignment capability.
Solution Approach 2:
The patent implements preliminary phase detection and error signal generation that enables proactive phase alignment. By detecting phase differences early and generating error signals before full synchronization is needed, the system can make incremental adjustments without requiring complete reset sequences, thereby maintaining continuous operation and high productivity.
2Stability of the object's composition
If reset function is employed to synchronize multiple flip-flops, then synchronization is achieved, but additional circuit overhead lowers the speed of each flip-flop
Solution Approach 1:
The patent replaces the mechanical reset mechanism with an electronic phase detection and control system. Instead of using reset signals that require additional circuit overhead and slow down flip-flops, the system uses phase error detection and continuous feedback control to achieve synchronization, thereby maintaining high operating speeds while ensuring reliable synchronization.
Solution Approach 2:
The patent implements feedback control where phase detection circuitry continuously monitors the phase relationship between clock signals, generates error signals based on detected phase differences, and feeds these back to adjust divider phases. This closed-loop feedback mechanism achieves reliable synchronization without requiring reset functions, thereby maintaining high flip-flop speeds.
3Reliability
If all clocks in a domain are reset for phase adjustment of one device, then phase consistency is maintained, but system utilization and efficiency are reduced
Solution Approach 1:
The patent segments the clock distribution system into independent controllable dividers, each capable of individual phase adjustment. This segmentation allows phase consistency to be maintained through localized adjustments rather than system-wide resets, thereby preserving system utilization and efficiency while ensuring phase reliability.
Solution Approach 2:
The patent implements dynamic phase adjustment capability where each divider can be independently tuned based on its specific phase requirements. This dynamic control allows the system to maintain phase consistency adaptively without requiring static reset sequences, enabling continuous operation at high utilization and efficiency levels.
Data Source
AI summary
Timing alignment circuits for use in synchronizing output signals of high-speed dividers and other clock generators are provided. An example timing alignment circuit includes detection circuitry to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a divide ratio slip signal. The example timing alignment circuit also includes control and aligning circuitry. The control circuitry receives a first local sync status signal and outputs a first control signal to a first component. The aligning circuitry receives the error sign signal and the divide ratio slip signal from the detection circuitry and also receives a second local sync status signal indicating when the first and second output signals are synchronized. The aligning circuitry outputs a second control signal to a second component that synchronously enables the output path receiving the clocks from different dividers with all rising edges aligned similar to a circuit exiting a synchronous reset.