High-Speed FPGA Configuration via MCU and Quad or Octal SPI Flash
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Solution Overview
Problem
Existing FPGA configurations face challenges in systems requiring flexibility and fast processing due to increased costs with active serial configuration and slow performance with passive serial configuration, especially in real-time applications like industrial imaging and video processing, which also result in high power consumption and lack remote update capabilities.
Innovation Solution
A system using an MCU with a standard SPI interface to support ×4/×8 passive serial FPGA configuration by coupling it with a single flash memory, allowing the MCU to initiate configuration and the FPGA to read the file, eliminating the need for separate interfaces and enabling faster, power-efficient updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If active serial FPGA configuration is used, then configuration speed and processing capability are improved, but system cost increases due to requiring separate external memory and programming interface
Solution Approach 1:
The patent combines the MCU firmware storage and FPGA configuration data storage into a single external flash memory device. The flash memory is partitioned to store both the MCU operating system/firmware and the FPGA configuration bitstream, eliminating the need for separate memory devices and reducing system cost while maintaining fast configuration speeds through the SPI interface.
Solution Approach 2:
The external flash memory device serves multiple functions: it acts as the program memory for the MCU, stores the FPGA configuration data, and provides fast read access for both MCU execution and FPGA configuration. This multi-functional use of a single memory device reduces component count and system complexity.
2Device complexity
If passive serial FPGA configuration is used, then system cost is reduced by using shared memory, but configuration speed becomes too slow for real-time processing
Solution Approach 1:
The patent merges the configuration data storage with the MCU's program memory in a single flash device, allowing the FPGA to read configuration data directly from the same memory that the MCU uses for its operating system, achieving both cost reduction and improved speed.
Solution Approach 2:
The configuration data is pre-loaded into the flash memory in a format that allows efficient reading. The flash memory is programmed with both the MCU firmware and FPGA configuration data during manufacturing, enabling fast read-out during operation without requiring slow serial transfer.
3Productivity
If FPGA remains in active user mode for real-time processing, then processing capability is maintained, but power consumption increases
Solution Approach 1:
The system uses periodic reconfiguration instead of continuous active operation. The FPGA can be configured, then placed in a low-power state, and reconfigured periodically when configuration updates are needed or when processing is required, significantly reducing average power consumption while maintaining real-time processing capability.
Solution Approach 2:
The MCU manages the FPGA's power state and reconfiguration autonomously. When processing is needed, the MCU reconfigures the FPGA from the shared flash memory and activates it; when not needed, the FPGA can be powered down or placed in retention mode, with the MCU controlling this lifecycle without external intervention.
Data Source
AI summary
A system to perform high speed passive serial configuration of an FPGA is disclosed. The system includes an MCU that includes an interface, an FPGA coupled to the MCU over the interface, and a flash memory coupled to the MCU and to the FPGA over the interface. The flash memory includes MCU firmware for the MCU and FPGA configuration data for the FPGA. To perform passive serial configuration of the FPGA, the MCU is operable to at least: configure the flash memory to an input/output (IO) mode, place the FPGA in a configuration mode, send a read command over the interface to the flash memory for the FPGA configuration data, and continuously provide a clock signal over the interface to the flash memory until the FPGA configuration data is entirely read.