High-Speed IC Layout With Multi-Layer Wiring to Cut Parasitics
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Solution Overview
Problem
The challenge of achieving high integration density and high operating speed in integrated circuits is hindered by parasitic components arising from reduced dimensions in semiconductor processes, which limit the increase in operating speed.
Innovation Solution
The integrated circuit design includes a structure with parallel-connected transistors, utilizing gate contacts and wiring patterns in multiple layers to minimize parasitic components, with gate contacts overlapping source/drain wiring patterns, and source/drain regions connected in opposite directions to reduce capacitance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of integrated circuits and devices is reduced to increase integration density, then integration density is improved, but parasitic components increase which limits operating speed
Solution Approach 1:
The patent utilizes multi-layer wiring structures (first wiring layer, second wiring layer, third wiring layer) to route signals in three-dimensional space. Gate wiring patterns in the first wiring layer overlap with source/drain wiring patterns in the second wiring layer, allowing simultaneous routing of gate signals and source/drain signals without increasing planar footprint. This vertical dimensionality enables reduced parasitic resistance and capacitance while maintaining high integration density.
Solution Approach 2:
The patent divides the circuit into multiple functional layers with dedicated wiring patterns for different signal types. Gate electrodes are segmented into multiple parallel structures, and source/drain regions are correspondingly segmented. This segmentation allows independent optimization of each segment's electrical characteristics, reducing overall parasitic effects while maintaining compact layout.
2Quantity of substance
If micro-patterns are used to reduce device size, then integration density is improved, but parasitic components are increased
Solution Approach 1:
The patent introduces intermediate wiring layers and contact structures as mediators between the active device regions and external connections. The first wiring layer with gate wiring patterns serves as an intermediary that distributes gate signals to multiple gate electrodes, while the second wiring layer with source/drain wiring patterns provides intermediate connection points before reaching external pads. These intermediary structures reduce the parasitic impact of direct micro-pattern connections.
Solution Approach 2:
The patent moves wiring patterns from a single-plane micro-pattern layout to a multi-layer three-dimensional arrangement. By placing gate wiring in the first wiring layer and source/drain wiring in the second wiring layer, the patent eliminates the need for closely spaced micro-pattern interconnections in the same plane, thereby reducing parasitic capacitance between adjacent conductors while maintaining compact device footprint.
Data Source
AI summary
An integrated circuit is provided. The integrated circuit includes: an active region extending in a first direction; gate electrodes extending in a second direction in parallel with each other; source/drain regions provided on the active region between the gate electrodes; a first gate contact connected to the gate electrodes and extending in the first direction; a first gate wiring pattern provided in a first wiring layer, electrically connected to the gate electrodes through the first gate contact, and overlapping the first gate contact along a third direction perpendicular to the first and second directions; and source/drain wiring patterns provided in a second wiring layer, electrically connected to the source/drain regions, respectively, extending in parallel with the second direction, and overlapping the source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer.