High Speed Short Reach I/O Interface With DC Balanced Coding
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Solution Overview
Problem
Conventional high bandwidth, short reach interconnections between chips or devices require significant power and chip area, making them undesirable for low power and small chip area circuits due to high power consumption and larger chip area requirements.
Innovation Solution
A high speed short reach input/output interface is implemented using on-package interfaces with transmitter and receiver circuits, a termination circuit comprising a shared capacitor and resistors, and a parallel coding block that encodes data using a DC balanced code, allowing for efficient data transmission with reduced power consumption and smaller chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional I/O interfaces are used for high bandwidth short reach interconnections, then signal transfer quality is maintained, but power consumption increases and chip area increases
Solution Approach 1:
The patent changes the electrical parameters of the I/O interface by using voltage swing reduction techniques and impedance matching optimizations. The transmitter circuit uses a reduced voltage swing (e.g., 0.6V instead of 1.2V) while maintaining signal integrity through careful parameter tuning of the driver strength, termination resistance, and channel compensation, thereby reducing power consumption while preserving signal transfer quality.
Solution Approach 2:
The patent implements dynamic voltage scaling and adaptive equalization techniques where the transmitter and receiver circuits adjust their operating parameters based on channel conditions. The receiver includes adaptive equalizers that dynamically compensate for channel losses, allowing the system to maintain signal quality across varying conditions while optimizing power consumption by only using higher power modes when necessary.
2Reliability
If conventional I/O interfaces are used for high bandwidth short reach interconnections, then signal transfer quality is maintained, but chip area increases
Solution Approach 1:
The patent merges multiple functions into integrated transmitter and receiver circuits that combine differential signaling, equalization, and impedance matching in single compact blocks. The on-package interface integrates the I/O circuits directly onto the processor die, eliminating the need for separate discrete components and reducing overall chip area while maintaining signal transfer quality through unified design optimization.
Solution Approach 2:
The patent uses advanced process technology scaling (e.g., moving to 65nm or smaller nodes) to reduce the physical size of the I/O circuits. By scaling the transistor dimensions and optimizing the layout of the differential pairs, termination resistors, and equalization circuits, the patent achieves significant chip area reduction while maintaining or improving signal transfer quality through enhanced control and reduced parasitic effects.
3Use of energy by moving object
If on-package interfaces with shared capacitor termination are used, then power consumption and chip area are reduced, but signal transfer quality must be maintained
Solution Approach 1:
The patent introduces AC coupling capacitors as intermediaries between the transmitter and receiver stages. These shared capacitors block DC voltage while allowing AC signal transmission, enabling the use of lower power voltage levels and simplified termination circuits. The capacitors act as mediators that maintain signal integrity across the interface while allowing the use of energy-efficient circuit topologies on both sides of the interface.
Solution Approach 2:
The patent implements precise control of the AC coupling capacitor values and their associated termination resistors to optimize the frequency response and impedance matching of the interface. By carefully selecting capacitor values (e.g., 100fF to 1pF) and termination resistance (e.g., 50Ω differential), the system maintains signal transfer quality across the intended frequency range while achieving the desired power consumption reduction through the simplified termination architecture.
Data Source
AI summary
Described is an apparatus which comprises: a plurality of transmitter circuits on a first die; a plurality of receiver circuits on a second die; a plurality of data transmission lines communicatively coupling the first die to the second die for the plurality of transmitter circuits to transmit data bits in parallel to the plurality of receiver circuits; a termination circuit comprising a shared capacitor and a plurality of resistors, each corresponding to one of the plurality of conductive lines and each coupled to the shared capacitor; and a parallel coding block to code data transmitted by the plurality of transmitter circuits via the plurality of data transmission lines according to a direct current (DC) balanced code.