High-Speed I/O Traces for Signal Integrity and Package Size
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Solution Overview
Problem
As Si technology advances, multi- and many-core processors require increased processor-to-processor and processor-to-memory bandwidth, but increasing I/O pins or data rate leads to cost and manufacturing challenges due to signal integrity issues and board size constraints, limiting the effectiveness of existing methods for high-volume manufacturing.
Innovation Solution
The implementation of high-speed I/O traces on integrated circuit package substrates that avoid plated through-hole structures, using stripline or microstrip configurations with ground and power planes as shields, and flexible signal-transmission cables to achieve high-speed data transfer without the encumbrance of plated through-hole couplings, allowing for smaller package sizes and higher data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of I/O pins is increased to improve bandwidth, then the processor-to-processor and processor-to-memory bandwidth is improved, but the package size and board space increase
Solution Approach 1:
The patent changes the electrical parameters of the transmission medium by eliminating plated-through-hole structures and using dedicated high-speed trace layers with controlled impedance, ground planes, and shielding. This allows existing I/O pins to operate at higher data rates (5-40 Gb/s) without increasing pin count or package size, effectively increasing bandwidth through parameter optimization rather than quantity increase.
2Quantity of substance
If the data rate is increased to improve bandwidth, then the processor-to-processor and processor-to-memory bandwidth is improved, but signal integrity issues increase due to reflections and crosstalk
Solution Approach 1:
The patent extracts and eliminates the plated-through-hole structures from the high-speed signal path, replacing them with dedicated high-speed trace configurations that avoid the discontinuities causing reflections and crosstalk. By removing the problematic PTH structures entirely from the signal path, signal integrity is maintained at higher data rates.
Solution Approach 2:
The patent introduces ground planes and shielding structures as intermediary elements between signal traces. These intermediaries act as reference planes and electromagnetic shields that reduce crosstalk and control impedance, thereby maintaining signal integrity at high data rates without requiring reduction in bandwidth.
3Ease of manufacture
If plated-through-hole structures are used for I/O connections, then manufacturing is simplified, but signal integrity deteriorates due to reflections and crosstalk at high data rates
Solution Approach 1:
The patent segments the signal transmission path into dedicated high-speed trace layers that are electrically isolated from plated-through-hole structures. By separating the high-speed signal path from the PTH network, the patent maintains manufacturing simplicity while eliminating the signal integrity problems caused by PTH discontinuities and crosstalk.
4Ease of manufacture
If traditional I/O configurations with plated-through-holes are used, then cost is reduced, but manufacturing reliability decreases for high-volume production
Solution Approach 1:
The patent changes the manufacturing parameters by eliminating complex PTH plating processes for high-speed I/O connections and replacing them with surface-mounted trace configurations. This parameter change simplifies the plating requirements, reduces manufacturing variability, and improves reliability for high-volume production while maintaining cost-effectiveness.
Data Source
AI summary
A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.