High-Speed Link Error Detection for False Packet Prevention

Solution Overview

Problem

High-speed links, such as 100 Gb/s Ethernet, face challenges in preventing false packet acceptance due to uncorrectable errors, which are difficult to identify with existing methods that require a tradeoff between latency and gate count, and small changes in signal-to-noise ratio significantly impact the mean time to false packet acceptance.

Innovation Solution

Measuring the symbol error rate and determining if it exceeds a threshold using statistical analysis to assess link safety, implementing a counter to estimate the symbol error ratio, and using this information to determine whether the link meets the desired mean time to false packet acceptance requirement, with the option to disconnect or pause the link when errors exceed a certain threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uncorrectable error marking is implemented to prevent false packet acceptance, then link safety is improved, but either latency increases or gate count increases

Engineering Contradiction:

Improvelink safetyVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by continuously monitoring the symbol error rate and identifying uncorrectable codewords before they can cause false packet acceptance. The system proactively marks uncorrectable codewords by corrupting sync headers in advance, preventing erroneous data from reaching the MAC layer. This approach ensures link safety without requiring high-latency error detection methods.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces complex mechanical error detection systems with a statistical monitoring approach. Instead of using high gate count circuits to identify uncorrectable codewords, the system uses a symbol error rate counter and statistical analysis to determine when error marking should occur. This substitution reduces hardware complexity while maintaining reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If high gate count is used to implement uncorrectable error marking with low latency, then link safety is improved, but device complexity increases

Engineering Contradiction:

Improvelink safetyVSAvoidgate count

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex mechanical error detection systems with a statistical monitoring approach. Instead of using high gate count circuits to identify uncorrectable codewords, the system uses a symbol error rate counter and statistical analysis to determine when error marking should occur. This substitution reduces hardware complexity while maintaining reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the approach from direct error marking to statistical parameter monitoring. By monitoring the symbol error rate as a parameter and comparing it against thresholds, the system can indirectly identify when uncorrectable errors are likely occurring. This parameter-based approach simplifies the hardware architecture compared to direct error analysis.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If low latency is used for uncorrectable error marking, then productivity is improved, but either gate count increases or link safety decreases

Engineering Contradiction:

Improvedata transmission efficiencyVSAvoidlink safety

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by continuously monitoring the symbol error rate and identifying uncorrectable codewords before they can cause false packet acceptance. The system proactively marks uncorrectable codewords by corrupting sync headers in advance, preventing erroneous data from reaching the MAC layer. This approach ensures link safety without requiring high-latency error detection methods.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by continuously monitoring the symbol error rate and using this information to adjust error marking decisions. The system feeds back the measured symbol error rate to the error marking logic, enabling dynamic adaptation to changing link conditions. This feedback mechanism maintains both low latency and high reliability by responding quickly to error conditions.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10374751B2Increasing communication safety by preventing false packet acceptance in high-speed links

Publication Date: 2019.08.06 INTEL CORP

AI summary

Methods, apparatus, and systems for preventing false packet acceptance in high-speed links. Under one aspect, correctable symbol errors are detected, and determination is made to whether a symbol error rate or ratio (SER) exceeds an SER threshold. In response to detection of such a condition, the link is disconnected or temporarily paused. The value for the SER threshold is determined using a statistical analysis of various link parameters to meet desired performance levels, such as a mean time to false packet acceptance (MTTFPA) of >approximately 15 billion years while providing a mean time to disconnect of >100 years.