Automatic Speed Negotiation Module for High-Speed Serial Interfaces
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Solution Overview
Problem
Newer serial protocols such as PCI Express Generation 2, 4 Gbps Fibre Channel, and 8 Gbps Fibre Channel have short speed negotiation windows, which are too short for slow software or programmable logic to handle effectively, leading to inefficient data rate negotiation in high-speed serial interfaces within programmable logic devices.
Innovation Solution
A hardware module within the physical coding sublayer of the serial interface for automatic speed negotiation, allowing the device to start at a high or low data rate and adjust to the highest reliable speed by stepping up or down, with error detection and delimiter patterns to facilitate rate changes, optimizing data rate configuration within the PCS portion of the transceiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software or programmable logic is used for speed negotiation, then flexibility and programmability are improved, but negotiation speed and latency are worsened
Solution Approach 1:
The patent replaces software-based speed negotiation with a hardware-based automatic speed negotiation module integrated into the PCS. This hardware module uses dedicated circuitry to perform speed negotiation in parallel with data transmission, eliminating the sequential processing delays inherent in software implementations. The module includes error detection logic and automatic rate adjustment circuitry that operates independently of the main processor, thereby reducing negotiation latency while maintaining adaptability to different protocols.
2Productivity
If the negotiation window is shortened to meet protocol requirements, then protocol compliance is improved, but negotiation reliability is worsened
Solution Approach 1:
The patent implements preliminary error detection and validation mechanisms within the automatic speed negotiation module. Before finalizing a speed negotiation, the module performs preliminary checks including error rate monitoring and signal quality assessment. This preliminary validation ensures that negotiated speeds are reliable while maintaining compliance with short negotiation windows. The module can abort negotiations that show signs of potential failure, preventing unreliable connections from being established.
3Device complexity
If speed negotiation is performed outside the serial interface, then interface simplicity is improved, but negotiation performance is worsened
Solution Approach 1:
The patent merges the speed negotiation functionality directly into the PCS (Physical Coding Sublayer) of the serial interface. The automatic speed negotiation module is integrated within the PCS, allowing it to access transmission parameters and error statistics directly without requiring external communication. This integration enables the negotiation to occur in parallel with encoding and decoding operations, significantly improving negotiation efficiency while adding only one modular component to the interface structure.
Data Source
AI summary
A serial interface for a programmable logic device includes receiver and transmitter portions, and an automatic speed negotiation module to adjust the data rates of both portions. The speed adjustment may be accomplished by adjusting the widths of the data paths in both portions. The speed adjustment occurs on receipt of a control signal generated elsewhere on the programmable logic device, or generated by the module. One reason for generating the control signal is the detection of data errors in the received data, or the detection of a delimiter pattern in the received data signifying that a remote device is about to change its data rate.Similarly, before changing its data rate, the module may insert a delimiter in the data in the transmitter portion. After receipt or transmission of a delimiter pattern, the module may wait for a predetermined delay period to elapse before changing the data rate.