High-Speed Signal Subsystem Testing via Loopback Impedance Profiling
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Solution Overview
Problem
Conventional In-Circuit Test (ICT) systems are inadequate for testing high-speed signal subsystems in information handling systems, as they cannot access buried stripline traces and suffer from limitations such as reflections, insertion losses, and inability to determine issues with high-speed differential traces, leading to costly and time-consuming disassembly and retesting processes.
Innovation Solution
A high-speed signal subsystem testing system that includes a processing system with a memory system executing instructions to generate test signals, transmit them through a loopback subsystem, receive results, process them to generate an impedance profile, and compare it to an expected profile to identify communication path issues, allowing for non-invasive testing of high-speed connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If conventional ICT systems are used to test signaling subsystems, then testing can be performed on accessible portions, but access to buried stripline traces and NPU BGA pads is prevented
Solution Approach 1:
The patent introduces SMT test point pads as intermediary access points on the circuit board surface that enable ICT probes to indirectly access and test buried stripline traces and NPU BGA pads without requiring physical access to those hidden components. The test point pads serve as mediators that transmit test signals through the circuit board traces to the inaccessible components.
Solution Approach 2:
The patent moves the test access points from the vertical dimension (requiring access to buried traces and pads) to the horizontal dimension (surface-mounted test point pads). This dimensional transformation allows ICT probes to access previously unreachable components by creating access points on the circuit board surface rather than attempting to reach into hidden traces.
2Ease of operation
If SMT test point pads are provided for accessible portions of traces, then some testing can be performed, but reflections, insertion losses, and return losses occur that prevent high-speed signal testing
Solution Approach 1:
The patent applies local quality by making the test point pads and associated trace sections electrically optimized for high-speed signaling in specific localized areas. The test points are designed with controlled impedance and minimized length to reduce their impact on signal integrity, allowing them to serve testing functions without significantly degrading high-speed signal transmission.
Solution Approach 2:
The patent creates electrical copies or models of the high-speed signal paths through the test point pads, allowing testing of signal characteristics without requiring the pads to be perfect high-speed transmission lines. The test system measures electrical properties that replicate what would be observed in actual high-speed operation.
3Productivity
If conventional ICT testing is performed with the switch device powered on or off, then testing can be conducted, but the NPU blocks access to BGA pads and breakout vias
Solution Approach 1:
The patent performs preliminary action by pre-configuring SMT test point pads and associated circuitry during circuit board manufacturing, before the NPU is mounted. This preliminary setup creates accessible test access points that remain available even after the NPU is soldered to the BGA pads, allowing subsequent testing without requiring NPU removal or disassembly.
4Reliability
If loopback modules are connected to QSFP ports for final device testing, then system-level testing can be performed, but disassembly and retesting are required when issues are found
Solution Approach 1:
The patent performs preliminary testing at the circuit board level using SMT test point pads before final device assembly and customer delivery. By testing individual traces, connectors, and signal paths separately at this earlier stage, potential issues are identified and resolved before the device is fully assembled and shipped, preventing costly disassembly and retesting cycles later.
Solution Approach 2:
The patent segments the testing process into separate, independent tests of individual circuit board components (traces, connectors, test points) rather than only testing the complete assembled device. This segmentation allows isolated identification of problematic components and enables targeted repairs or replacements without requiring complete device disassembly.
Data Source
AI summary
A high-speed signal subsystem testing system includes a processing system having a transmitter and a receiver, a loop back subsystem coupled to the transmitter and receiver to provide a testing communication path between the transmitter and the receiver, and a communication path testing engine coupled to the transmitter and the receiver. The communication path testing engine generates test signal(s) and transmits the test signal(s) via the transmitter and through the testing communication path provided by the loop back subsystem and, in response, receives test signal result(s) via the receiver and through the testing communication path provided by the loop back subsystem, The communication path testing engine processes the test signal result(s) to generate a testing impedance profile for the testing communication path, and compares the testing impedance profile to an expected impedance profile to determine whether a testing communication path issue exists in the testing communication path.