High-Speed Storage Device Connectors With Re-Timers for Multi-Level Signaling

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Solution Overview

Problem

Existing U.2 connectors face limitations in accommodating higher data transfer rates and signal speeds due to the challenges of multi-level signaling, leading to increased costs and noise susceptibility, which conventional techniques struggle to address effectively.

Innovation Solution

Implementing a multi-protocol storage device connector with a U.2 connector capable of high-speed multi-level signaling, such as a SAS4 U.2 connector, and using a midplane with re-timers and high-speed connectors to facilitate data transfers through Ethernet and PCIe protocols, along with re-timing signals to enhance signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional U.2 connectors are used for data storage devices, then compatibility with multiple storage protocols (SATA, SAS, NVMe) is achieved, but the connector cannot effectively accommodate higher data transfer rates and signal speeds due to multi-level signaling challenges

Engineering Contradiction:
Improvedata transfer rateVSAvoidsignal integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces re-timers as intermediary devices positioned between the U.2 connector and the storage device. These re-timers actively regenerate and clean up multi-level signaling signals (such as PAM4 signals used in SAS4 and PCIe Gen6), compensating for signal degradation and noise accumulation that occur at higher data transfer rates. This intermediary component enables reliable high-speed communication without requiring fundamental changes to the U.2 connector standard.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multi-level signaling protocols are implemented to achieve higher data transfer rates, then productivity is improved, but noise susceptibility increases and system complexity rises

Engineering Contradiction:
Improvedata transfer throughputVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The re-timer acts as a specialized intermediary that handles the complexity of multi-level signaling internally. It receives degraded multi-level signals from the U.2 connector, performs equalization and regeneration, and outputs clean signals to the storage device. This approach allows the system to benefit from high-speed multi-level signaling protocols (achieving 12-20 Gb/s per lane) without requiring every component in the signal path to be redesigned for high-speed operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent leverages parameter changes in the signaling protocol itself, specifically adopting pulse amplitude modulation level-4 (PAM4) signaling which encodes two bits per symbol. This parameter change in the modulation scheme doubles the theoretical data rate compared to traditional NRZ signaling, enabling the U.2 connector to achieve SAS4 speeds (12 Gb/s per lane) and PCIe Gen6 speeds (16 Gb/s per lane) through the same physical interface.

Inventive Principle:
Principle #35Parameter changes

3Speed

If multi-level signaling is used to increase data transfer speed, then productivity improves, but noise susceptibility increases

Engineering Contradiction:
Improvesignal speedVSAvoidnoise susceptibility
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The re-timer serves as a noise-filtering intermediary in the signal path. It actively monitors incoming multi-level signals, identifies and corrects errors caused by noise and interference, and regenerates clean signals. This is particularly important for multi-level signaling where voltage levels are more closely spaced, making signals more vulnerable to noise. The re-timer effectively extends the usable signal distance and improves reliability in electrically noisy data center environments.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12399657B2High-speed data transfers through storage device connectors
Publication Date: 2025.08.26 SAMSUNG ELECTRONICS CO LTD
  • US12399657B2 patent drawing
  • US12399657B2 patent drawing
  • US12399657B2 patent drawing

AI summary

Data storage systems, devices and methods may use a switch board configured to communicate using a high-speed multi-level signaling protocol, and a midplane having one or more multi-protocol storage device connectors configured to couple the midplane to one or more storage devices, wherein the midplane may be coupled to the switch board and configured to enable the one or more storage devices to communicate with the switch board through the one or more multi-protocol storage device connectors using the high-speed multi-level signaling protocol. The midplane may be coupled to the switch board through one or more high-speed connectors. One or more re-timers may be coupled between one or more of the high-speed connectors and one or more of the multi-protocol storage device connectors. One or more cables may be used to transfer data to and from the multi-protocol storage device connectors.