High-Speed FET Switch Gate Reset for Capacitive Load Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed switches used for handling high power signals face challenges with increased switching time due to parasitic capacitance and capacitive loading at the outputs of the drivers switching the FET gates.
Innovation Solution
A method and apparatus that involve resetting the gate of the field effect transistor (FET) to a reference potential before activating or deactivating the switch, thereby minimizing the loading effect on the power supply and reducing switching time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If large switches are implemented using stacked field effect transistors to handle high power signals, then power handling capability is improved, but switching time increases due to parasitic capacitance and capacitive loading
Solution Approach 1:
The patent applies preliminary action by resetting the gate of the FET to a reference potential before the actual switching operation. This pre-action clears accumulated charge on the gate, reducing the capacitive loading effect that would otherwise slow down the switching transition. The reset occurs in advance of the main switching event, preparing the FET for faster activation or deactivation.
Solution Approach 2:
The patent changes the electrical parameter of the gate potential by introducing a reset phase that temporarily sets the gate to a reference potential (different from the normal operating potentials). This parameter change reduces the effective capacitance loading during the subsequent switching operation, enabling faster switching while maintaining the same power handling capability through the stacked FET configuration.
2Ease of operation
If the gate of the FET is driven directly without resetting, then the switch can be activated or deactivated, but the accumulated charge on the gate increases the switching time
Solution Approach 1:
The reset operation is performed as a preliminary action before the actual switch activation or deactivation. By clearing the gate charge in advance, the system prepares the FET for a faster response to the subsequent drive signal, reducing the overall switching time while maintaining ease of operation through automated reset control.
Solution Approach 2:
The reset circuit applies a preliminary anti-action by opposing the accumulation of charge on the gate that would otherwise slow down switching. The reset phase actively removes charge buildup before it can significantly impact the switching speed, counteracting the capacitive loading effect in advance of the main switching operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the switching time of high-speed switches by minimizing the loading effect on the power supply, thereby improving the overall performance of switches handling high power signals.
Implementation Method 1
parasitic capacitance and capacitive loading at the outputs of the drivers switching the FET gates
Data Source
AI summary
A method and apparatus is disclosed for maintaining a stable power supply to a circuit when activating/deactivating a switch in order to accelerate the switching time of the switch. The gate of a FET is coupled to a switch driver. The switch driver is powered by a positive power supply and a negative power supply. When the switch is to be activated/deactivated, the gate is first coupled to a reference potential (i.e., ground) for a “reset period” to reduce any positive/negative charge that has been accumulated in the FET. At the end of the reset period, the gate is then released from the reference potential and the switch driver drives the gate to the desired voltage level to either activate or deactivate the switch.