High-Speed Debug Trace Offloading for On-Chip Memory Preservation
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Solution Overview
Problem
Modern integrated circuits face challenges in efficiently collecting and storing trace data from various compute circuits due to the large quantities generated, which occupy on-chip memory resources, affecting user designs and limiting their size or operation.
Innovation Solution
A high-speed debug port trace circuit offloads trace data from multiple compute circuits to an external storage device, using programmable circuitry to packetize and transmit data via a high-speed communication link, avoiding the need for on-chip memory storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If on-chip memory is used to store trace data, then trace data storage capacity is improved, but on-chip memory resources become unavailable for user designs
Solution Approach 1:
The patent extracts the trace data storage function from the on-chip memory system and relocates it to an external memory device. The debug port trace circuit captures trace data and transmits it externally, separating the storage burden from the on-chip resources. This allows on-chip memory to remain available for user designs while providing substantial trace data storage capacity through external memory.
2Extent of automation
If on-chip programmable logic resources are used to implement trace data collection, then trace data collection capability is improved, but programmable logic resources become unavailable for user circuit designs
Solution Approach 1:
The patent extracts the trace data collection and transmission functionality into a dedicated debug port trace circuit, separating it from the programmable logic resources. This dedicated circuit handles all trace data collection, packetization, and external transmission, freeing up programmable logic resources to be fully available for user circuit designs while maintaining comprehensive trace data collection capability.
3Duration of action of moving object
If large amounts of trace data are stored on-chip, then trace data storage window is improved, but user design size is limited
Solution Approach 1:
The patent extends the trace data storage capacity by moving from the on-chip dimension to the external system dimension. By transmitting trace data through a high-speed communication link to external memory, the system achieves virtually unlimited storage window without constraining the on-chip area available for user designs. The storage window is now determined by external memory capacity rather than on-chip memory size.
Data Source
AI summary
Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace data originate. Debug trace packets (DTPs) are generated from the trace data and transmitted over a high-speed communication link to a trace data storage device (TDSD) external to the IC. Within the TDSD, trace data from the DTPs are stored in a memory of the TDSD.