High-Temperature Metallization With Plated Interlayer PCB Transfer

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Solution Overview

Problem

Conventional printed circuit boards face issues with high electrical resistance and require numerous manufacturing steps due to the use of organic insulating materials and etching processes, leading to inefficiencies in forming multilayer structures.

Innovation Solution

The method involves forming a conductor pattern and interlayer conductor projections on a temporary circuit holding material through electroless and electrolytic plating, then transferring these features to a true circuit holding material, eliminating the need for drilling and reducing the number of manufacturing steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional etching and organic insulating materials are used, then manufacturing processes are simplified, but electrical resistance increases and manufacturing steps multiply

Engineering Contradiction:
Improveelectrical resistanceVSAvoidmanufacturing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces conventional mechanical etching processes with a plating-based formation method. Conductive patterns and interlayer conductor projections are formed through electroless and electrolytic plating on a temporary circuit holding material, then transferred to the true circuit holding material. This substitution eliminates the need for multiple etching steps and reduces overall manufacturing complexity while achieving lower electrical resistance through direct metal deposition.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent performs preliminary plating actions on a temporary circuit holding material before final transfer. The conductor patterns and interlayer conductor projections are pre-formed through electroless plating followed by electrolytic plating, allowing these features to be embedded directly into the true circuit holding material during the transfer process, thereby reducing subsequent manufacturing steps.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple layers are formed by conventional methods, then circuit functionality is achieved, but manufacturing time and process steps increase

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidmanufacturing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent merges the formation of conductor patterns and interlayer conductor projections into a single integrated plating process. Both features are formed simultaneously through electroless plating followed by electrolytic plating on the temporary circuit holding material, and both are transferred together to the true circuit holding material in one transfer operation, significantly reducing the number of separate manufacturing steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a temporary circuit holding material as an intermediary substrate. This temporary material serves as a platform for forming conductor patterns and interlayer conductor projections through plating, then the entire assembly is transferred to the true circuit holding material. This intermediary approach consolidates multiple formation steps into one transfer operation, improving productivity and reducing manufacturing time.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If conventional plating methods are used, then conductor formation is achieved, but electrical resistance remains high

Engineering Contradiction:
Improveelectrical resistanceVSAvoidconductor formation process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies electroless plating as a preliminary action before electrolytic plating. The electroless plating creates an initial conductive layer that provides nucleation sites for subsequent electrolytic plating, ensuring uniform and low-resistance metal deposition. This two-stage plating approach achieves lower electrical resistance compared to conventional single-step plating methods.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces conventional high-resistance conductor formation methods with a controlled plating process. By using electroless plating followed by electrolytic plating, the invention achieves denser, more uniform metal deposits with lower electrical resistance, while the entire process is integrated into the temporary circuit holding material framework for ease of manufacture.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces electrical resistance and simplifies the manufacturing process by embedding conductor patterns and projections directly onto the true circuit board, resulting in a more efficient and cost-effective multilayer printed circuit board.

Implementation Method 1

forming a conductor pattern and interlayer conductor projections on a temporary circuit holding material through electroless and electrolytic plating

Methodology Applied
Scientific EffectElectroless plating: Electroplating

Implementation Method 2

forming a conductor pattern and interlayer conductor projections on a temporary circuit holding material through electroless and electrolytic plating

Methodology Applied
Scientific EffectElectrolytic plating: Electroplating

Data Source

PatentUS20260047420A1High temperature metallization
Publication Date: 2026.02.12 3D GLASS SOLUTIONS INC
  • US20260047420A1 patent drawing
  • US20260047420A1 patent drawing

AI summary

Provided herein is a high temperature metallization structure with a refractory diffusion barrier for high-speed computing, RF, High Temperature Controls, and mmWave electronics and components.