High Thermal Conductivity Substrate for Semiconductor Devices

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Solution Overview

Problem

High-speed group III-Nitride semiconductor devices face challenges with heat dissipation due to the limited thermal conductivity of conventional Silicon-Carbon substrates, leading to poor manufacturability and thermal performance, especially in high-power applications.

Innovation Solution

A semiconductor device design featuring a high thermal conductivity substrate with a heat sink carrier and a channel structure, where the substrate has a thermal conductivity greater than 400 W/mK, formed using materials like diamond, and a process involving a heat sink carrier, high thermal conductivity substrate, and channel structure to enhance thermal performance without increasing device size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SiC substrate is used for high-speed group III-Nitride semiconductor device, then device operation speed is improved, but thermal conductivity is insufficient leading to poor heat dissipation

Engineering Contradiction:
Improveoperation speedVSAvoidheat dissipation
Core Design Contradiction:
SpeedVSTemperature

Solution Approach 1:

The patent uses a composite structure combining SiC substrate with a high thermal conductivity layer (diamond or cubic silicon carbile) to achieve both high electron mobility for fast operation and high thermal conductivity for effective heat dissipation. The composite material approach allows leveraging the electrical properties of SiC while adding thermal management capabilities through the high thermal conductivity layer.

Inventive Principle:
Principle #40Composite materials

2Reliability

If ex situ transition layer is added to achieve reliable bonding, then bonding reliability is improved, but thermal barrier is created reducing heat dissipation

Engineering Contradiction:
Improvebonding reliabilityVSAvoidthermal barrier
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent changes the approach from using ex situ transition layers to using in situ grown transition layers, fundamentally altering the bonding method. The in situ growth allows direct epitaxial growth of the channel structure on the high thermal conductivity layer, eliminating the need for separate transition layers and their associated thermal barriers while maintaining bonding reliability.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If temporary handling wafer is used to hold etched device, then device handling is improved, but process complexity increases and manufacturing difficulty arises

Engineering Contradiction:
Improvedevice handlingVSAvoidprocess complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent inverts the conventional process sequence by growing the high thermal conductivity layer and channel structure in situ before substrate removal, rather than etching the substrate first and then handling the delicate membrane. This inversion eliminates the need for temporary handling wafers and complex manipulation steps, simplifying the overall manufacturing process.

Inventive Principle:
Principle #13The other way round (Inversion)

4Temperature

If diamond deposition is performed at high temperature, then high thermal conductivity substrate is formed, but temporary handling wafer cannot withstand the temperature

Engineering Contradiction:
Improvedeposition temperatureVSAvoidwafer withstand capability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent performs the high-temperature diamond deposition in situ directly on the SiC substrate before any substrate removal or handling steps. By completing the high thermal conductivity layer formation while the substrate is still intact and providing thermal support, the process avoids subjecting temporary handling wafers to temperatures they cannot withstand.

Inventive Principle:
Principle #10Preliminary action

5Temperature

If SiC substrate is etched away to form high thermal conductivity substrate, then thermal conductivity is improved, but manufacturing complexity and difficulty increase

Engineering Contradiction:
Improvethermal conductivityVSAvoidmanufacturability
Core Design Contradiction:
TemperatureVSEase of manufacture

Solution Approach 1:

The patent merges the formation of the high thermal conductivity layer with the channel structure growth in an in situ process. By combining these steps into a single epitaxial growth process, the patent eliminates multiple separate manufacturing steps including substrate etching, transition layer deposition, and device reattachment, significantly improving manufacturability while achieving the desired thermal conductivity enhancement.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively enhances the thermal performance of semiconductor devices, addressing heat dissipation issues and improving manufacturability by utilizing a high thermal conductivity substrate and heat sink carrier, resulting in improved power and reliability performance.

Implementation Method 1

The high thermal conductivity substrate has a thermal conductivity greater than 400 W/mK

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10090172B2Semiconductor device with high thermal conductivity substrate and process for making the same
Publication Date: 2018.10.02 QORVO US INC
  • US10090172B2 patent drawing
  • US10090172B2 patent drawing
  • US10090172B2 patent drawing

AI summary

The present disclosure relates to a process of forming a semiconductor device with a high thermal conductivity substrate. According to an exemplary process, a semiconductor precursor including a substrate structure, a buffer structure over the substrate structure, and a channel structure over the buffer structure is provided. The channel structure has a first channel surface and a second channel surface, which is opposite the first channel surface, adjacent to the buffer structure, and has a first polarity. Next, a high thermal conductivity substrate with a thermal conductivity greater than 400 W/mK is formed over the first channel surface. A heat sink carrier is then provided over the high thermal conductivity substrate. Next, the substrate structure and the buffer structure are removed to provide a thermally enhanced semiconductor device with an exposed surface, which has the first polarity.