High Voltage Semiconductor Barrier Region Leakage Reduction
Solution Overview
Problem
The semiconductor industry faces challenges in developing high voltage devices with reduced leakage, particularly in advanced technologies below 45 nm, where high implantation concentrations can lead to punch-through and resistance issues, affecting device reliability.
Innovation Solution
A semiconductor device and method involving a semiconductor substrate with a gate structure, sidewall spacers, source and drain regions, and a barrier region formed by doping a dopant of a different conductivity type, which reduces leakage and improves reliability by forming a barrier that self-aligns with the gate structure, allowing for concurrent fabrication with low voltage devices without additional masks or processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high implantation concentration is used to prevent punch-through and reduce source/drain resistance, then device reliability improves, but leakage current increases
Solution Approach 1:
The source/drain region is segmented into multiple doped regions with different conductivity types and concentrations. Specifically, a first doped region (e.g., n-type) and a second doped region (e.g., p-type) are formed adjacent to the channel, creating a segmented structure that prevents punch-through while reducing leakage through the alternating polarity regions
Solution Approach 2:
Different regions of the source/drain structure are assigned different doping qualities. The first doped region has one conductivity type and concentration optimized for preventing punch-through, while the second doped region has opposite conductivity type to reduce leakage, creating local quality variations that address both problems simultaneously
2Area of moving object
If scaling down of logic devices continues with advanced technologies, then circuit density improves, but process complexity increases
Solution Approach 1:
The formation of multiple doped regions with different conductivity types is merged into a single ion implantation process step. By using alternating polarity implants in sequence without requiring additional photolithography masks or process steps, the patent combines what would traditionally be separate fabrication operations into one integrated process flow
Solution Approach 2:
The alternating polarity doping regions self-align with the gate structure through the ion implantation process itself, eliminating the need for additional alignment steps or masks. The process serves itself by using the gate structure as a natural alignment reference, reducing overall process complexity
3Reliability
If high implantation concentration is used to reduce source/drain resistance, then conductivity improves, but leakage problems worsen
Solution Approach 1:
Instead of using uniform high-concentration doping that causes leakage, the patent inverts the approach by using alternating polarity doping regions. The second doped region with opposite conductivity type acts as a barrier that inverts the leakage problem, allowing high implantation concentration in the first region to improve conductivity without the harmful leakage effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces off-state current (leakage) and enhances time-dependent dielectric breakdown (TDDB) reliability, improving DC performance and hot carrier injection lifetime, while maintaining compatibility with CMOS process flows for logic devices, thus addressing the complexity of integrating high voltage and low voltage devices on a single chip.
Implementation Method 1
a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity
Data Source
AI summary
A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.