High-Voltage Semiconductor Structure for Compact Breakdown Control
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Solution Overview
Problem
Existing high voltage semiconductor devices, such as LDMOS transistors, face challenges in achieving a balance between high breakdown voltage and small size, while maintaining efficient switching speed and sufficient depletion layer formation.
Innovation Solution
The semiconductor device incorporates a first conductive type buried layer with a unique structure, comprising a first region and a second region, where the second region is formed on top of the first region and has a top surface closer to the substrate surface, allowing direct contact with the first conductive type deep well region and optimizing the depletion layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thick P-type epitaxial layer is formed to achieve sufficient depletion layer for high voltage, then breakdown voltage is improved, but the N-type deep well region cannot bond to the N-type buried layer, affecting device function
Solution Approach 1:
The P-type epitaxial layer is segmented into two distinct regions: a first P-type region with higher resistivity and thinner thickness, and a second P-type region with lower resistivity and greater thickness. This segmentation allows the first region to enable proper bonding between the N-type deep well and N-type buried layer, while the second region provides sufficient depletion layer thickness for high breakdown voltage performance.
2Strength
If the P-type epitaxial layer thickness is increased to improve breakdown voltage, then withstand voltage is improved, but the device size increases
Solution Approach 1:
Different regions of the P-type epitaxial layer are assigned different local properties: the first P-type region has higher resistivity and is positioned to facilitate bonding, while the second P-type region has lower resistivity and greater thickness to provide adequate depletion layer for voltage withstand. This local differentiation allows optimized performance without increasing overall device footprint.
3Strength
If a typical RESURF structure with N-type deep well region bonded to N-type buried layer is used, then withstand voltage is improved, but manufacturing complexity increases due to precise bonding requirements
Solution Approach 1:
The P-type epitaxial layer is divided into a first P-type region with higher resistivity and a second P-type region with lower resistivity. The first region is specifically designed to facilitate bonding between the N-type deep well and N-type buried layer by providing appropriate electrical properties, thereby reducing bonding complexity and improving ease of manufacture while maintaining high withstand voltage through the second region.
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.