High-Voltage Tolerant CMOS Input Circuit Without Static Current
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Solution Overview
Problem
Existing electronic devices face challenges in interfacing different voltage domains efficiently, particularly in operating at both high and low supply voltage levels without significant leakage current, area inefficiency, and high manufacturing costs, as described in U.S. Pat. Nos. 6,768,339 B2 and 6,771,113 B1.
Innovation Solution
A high-voltage tolerant circuit design utilizing parallel NMOS and PMOS transistors with specific gate and substrate couplings, along with an additional NMOS transistor for clamping, to ensure safe signal passage across varying voltage levels without static current, implemented in a process technology without native devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a native pass gate is used to interface voltage domains, then high voltage tolerance is achieved, but device cost increases significantly and not all process technologies support native devices
Solution Approach 1:
The patent replaces expensive native devices with standard CMOS transistors that are already available in all process technologies. The solution uses conventional transistors with carefully designed gate and substrate connections to achieve high voltage tolerance without requiring special native device fabrication processes, thereby significantly reducing device cost while maintaining manufacturing compatibility.
Solution Approach 2:
The patent changes the electrical parameters of standard CMOS transistors by connecting substrates to different voltage potentials (VSS for NMOS, VDD for PMOS) and adjusting gate voltages dynamically. This parameter modification enables standard transistors to tolerate high input voltages up to VDD + VOV without requiring native device characteristics, thus achieving high voltage tolerance through parameter control rather than special device structures.
2Reliability
If a source follower configuration with resistors is used for high voltage tolerance, then high voltage protection is achieved, but constant static current flows creating power inefficiency
Solution Approach 1:
The patent employs dynamic switching of transistor gates based on input voltage levels. The NMOS transistor gate is connected to VDD and the PMOS transistor gate is connected to the input signal, enabling the transistors to switch between different operating states. This dynamic operation allows the circuit to pass high voltage signals when needed while minimizing static current flow during normal operation, thereby achieving both high voltage protection and power efficiency.
Solution Approach 2:
The patent removes the constant static current path inherent in source follower configurations by using a different circuit topology. Instead of relying on resistive loads that continuously draw current, the solution uses transistor switches that only conduct when actively switching signals, extracting the harmful static current component while retaining the high voltage protection function.
3Reliability
If a switch CMOS pass gate is used for 5V tolerant input, then high voltage tolerance is achieved, but circuit complexity increases and additional control signals are required
Solution Approach 1:
The patent makes standard CMOS transistors perform multiple functions: signal passing, high voltage tolerance, and level shifting. By connecting the NMOS substrate to VSS and the PMOS substrate to VDD, and by appropriately biasing the gates, the same transistor structure handles both low voltage signal integrity and high voltage protection without requiring separate dedicated circuits for each function, thereby reducing overall circuit complexity.
Solution Approach 2:
The patent combines the high voltage protection function with the signal passing function into a single transistor stage. Instead of using separate protection circuits and pass gates, the solution merges these functions by designing the transistor biasing and substrate connections to simultaneously provide high voltage tolerance and efficient signal transmission, eliminating the need for additional control signals and reducing circuit complexity.
Data Source
AI summary
An electronic device is provided with a high-voltage tolerant circuit. The high-voltage tolerant circuit comprises an input terminal for receiving an input signal (VIN), a first node (A) and a second node (B), wherein the second node (B) is coupled to an input of a receiver (R). The high-voltage tolerant circuit furthermore comprises a first NMOS transistor (N1) and a first PMOS transistor (P1) coupled in parallel between the input terminal and the second node(B). Furthermore, a second PMOS transistor (P2) is coupled between the input terminal and node A and a second NMOS transistor is coupled with one of its terminals to the first node. The gate of the first NMOS transistor (N2) is coupled to a supply voltage (VDDE). The gate of the first PMOS transistor (P1) is coupled to the first node (A). The gate of the second NMOS transistor (N2) and the gate of the second PMOS transistor (P2) are coupled to the supply voltage (VDDE).