High Voltage CMOS Device Isolation via Separated Wells
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Solution Overview
Problem
The existing methods for fabricating high-voltage CMOS devices are time-consuming and costly, requiring additional processing steps and longer times due to the need for epitaxial layers and different well structures for high-voltage and low-voltage devices, which complicates integration on a single substrate.
Innovation Solution
The solution involves forming high-voltage transistors with P-wells and N-wells separated by a distance, allowing for simultaneous fabrication with low-voltage transistors using shared process steps, including deep N-wells and doped isolation regions, which reduces processing time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial layers and separate well structures are used for high-voltage devices, then device performance and isolation are improved, but manufacturing complexity and processing time increase
Solution Approach 1:
The patent combines high-voltage and low-voltage device fabrication into a single integrated process. The P-well and N-well are formed in the same epitaxial layer using shared implantation and oxidation steps, eliminating the need for separate processing streams. This merging of previously distinct fabrication sequences reduces manufacturing complexity while maintaining the isolation benefits of the epitaxial structure.
Solution Approach 2:
The patent creates a universal fabrication process that serves both high-voltage and low-voltage device requirements simultaneously. The same epitaxial layer, well formation techniques, and isolation structures fulfill the needs of both device types, making the manufacturing process multi-functional and eliminating the need for specialized separate processes.
2Reliability
If epitaxial layers are grown for high-voltage devices, then device performance is improved, but production time and cost increase
Solution Approach 1:
The patent implements continuous processing where the epitaxial layer growth, well formation, and isolation steps proceed in an unbroken sequence without interruption or separate processing cycles. The fabrication flow moves continuously through all stages, maximizing equipment utilization and reducing production time while maintaining the quality benefits of epitaxial growth.
Solution Approach 2:
The patent performs preliminary actions by forming both P-well and N-well regions during the same epitaxial growth phase, rather than sequentially. The implantation and oxidation steps are prepared and executed in advance for both device types simultaneously, reducing overall production time while ensuring proper device performance.
3Reliability
If high-voltage and low-voltage devices are fabricated separately, then each device type achieves optimal performance, but integration on single substrate becomes complex
Solution Approach 1:
The patent applies local quality by creating region-specific device characteristics within a unified fabrication process. Different areas of the substrate receive tailored implantation doses, oxidation times, and well depths appropriate for either high-voltage or low-voltage devices, while the overall process remains integrated. This allows optimal performance for each device type without requiring separate manufacturing lines.
Data Source
AI summary
A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.