High Voltage Decoupling Capacitor Using Vertical Trench Isolation
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Solution Overview
Problem
Existing decoupling capacitors in semiconductor devices face challenges in achieving high breakdown voltages due to physical space constraints, making it difficult to isolate high voltage differences between electrical circuits effectively.
Innovation Solution
A decoupling capacitor design that integrates a first conductive layer into a substrate isolation region, with multiple dielectric layers and a second conductive layer overlapping the first, allowing for high voltage operation without additional metallization layers and minimizing lateral space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a decoupling capacitor is fabricated in the metallization layers or back end of line (BEOL) layers, then the capacitor can be integrated into the circuit, but the breakdown voltage is insufficient for high voltage differences of several kilovolts
Solution Approach 1:
The patent transitions the capacitor fabrication from horizontal planar metallization layers to a vertical three-dimensional structure using deep trench isolation regions. This dimensional change allows the capacitor to achieve high breakdown voltage through increased vertical separation distance without requiring additional horizontal metallization layers, thus resolving the contradiction between reliability and device complexity.
2Reliability
If a decoupling capacitor with high breakdown voltage is implemented, then galvanic isolation of high voltage differences can be achieved, but physical space constraints make it difficult to implement
Solution Approach 1:
The invention moves the capacitor structure from a two-dimensional planar layout to a three-dimensional vertical configuration by etching deep trenches into the substrate and filling them with dielectric material. This allows the electric field to be distributed vertically through multiple dielectric layers rather than horizontally, achieving high breakdown voltage while minimizing lateral footprint.
Solution Approach 2:
The capacitor structure is nested within the deep trench isolation region, utilizing the vertical space inside the trench to accommodate multiple stacked dielectric layers and conductive plates. This nesting approach allows the capacitor to be embedded within the substrate structure without occupying additional lateral area, resolving the space constraint contradiction.
3Reliability
If additional metallization layers are added to increase breakdown voltage, then high voltage operation is enabled, but the device layout space is consumed
Solution Approach 1:
Instead of adding more horizontal metallization layers to increase breakdown voltage, the patent creates a vertical stack of dielectric and conductive layers within the deep trench. This vertical stacking achieves the required voltage isolation by increasing the separation distance in the vertical dimension while keeping the horizontal footprint compact, thus avoiding consumption of additional device layout space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a high breakdown voltage capability while maintaining a compact device layout, enabling effective galvanic isolation between electrical circuits without consuming additional space.
Implementation Method 1
A decoupling capacitor may be used to galvanically isolate different electrical circuits of an electrical system to prevent stray currents from flowing
Implementation Method 2
A plurality of dielectric layers is arranged over the first isolation region
Data Source
AI summary
A capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate and a plurality of dielectric layers over the first isolation region. The plurality of dielectric layers may include inter layer dielectric (ILD) and inter metal dielectric (IMD) layers. The first conductive layer is a bottom plate of the capacitor. A second conductive layer is arranged over the plurality of dielectric layers, whereby the second conductive layer is a top plate of the capacitor and at least partially overlaps with the first conductive layer.