High Voltage Device Rdson Reduction via Local Quality
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Solution Overview
Problem
Conventional techniques for reducing drain-to-source on-resistance (Rdson) in lateral double-diffused transistors lead to higher impact ionization, compromising device reliability and performance.
Innovation Solution
The design incorporates a high voltage device with a substrate having a device region with source and drain regions, a gate between them, and first and second device wells, along with isolation regions, including device isolation and internal isolation structures, to reduce Rdson and impact ionization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques are used to reduce drain-to-source on-resistance (Rdson), then Rdson decreases, but impact ionization increases compromising device reliability
Solution Approach 1:
The patent applies local quality by creating distinct doped regions with different properties: a first doped region adjacent to the drain, a second doped region adjacent to the source, and a third doped region in the channel. Each region has specific doping concentrations and depths tailored to its function - the first region manages high electric fields near the drain, the second region controls carrier injection, and the third region maintains channel conductivity, collectively reducing impact ionization while maintaining low Rdson
Solution Approach 2:
The patent employs parameter changes by precisely controlling doping concentrations, diffusion depths, and geometric dimensions of the doped regions. The first doped region has a doping concentration of 1E16-1E18 atoms/cm³ extending to a depth of 0.5-2.0 micrometers, while the second doped region has 1E18-1E20 atoms/cm³ at 0.1-0.5 micrometers depth. These parameter optimizations enable the device to achieve low Rdson without excessive impact ionization
2Speed
If Rdson is reduced to improve switching speeds, then switching speeds increase, but energy loss during switching increases
Solution Approach 1:
The patent optimizes the balance between switching speed and energy loss by adjusting key parameters: the channel length (L) is controlled at 1-5 micrometers to enable fast switching, while the doping concentrations and depths of the three doped regions are precisely tuned to minimize resistive losses. The first doped region extends deeper (0.5-2.0 μm) to reduce series resistance, while the channel region maintains appropriate conductivity, achieving low Rdson without excessive power dissipation
Data Source
AI summary
High voltage devices and methods for forming thereof are disclosed. A high voltage device includes a substrate having a device region, where the device region includes a source region and a drain region defined thereon. A transistor is disposed on the device region. The transistor includes a gate disposed over the substrate and in between the source and drain regions. First and second device wells are disposed in the substrate within the device region. The first device well is adjacent to a second side of the gate and the second device well is adjacent to a first side of the gate. Isolation regions are disposed within the substrate. The isolation regions include a device isolation region surrounding the device region and one or more isolation fingers disposed in a first portion of the device region adjacent to the first side of the gate.