High Voltage Power Diode Guard Ring Structure for Breakdown Voltage
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Solution Overview
Problem
High voltage power diodes face challenges in achieving high breakdown voltage and suppressing parasitic current, particularly when used in high current applications, leading to low efficiency and latch-up issues.
Innovation Solution
The design incorporates a P-type semiconductor substrate with a P-type epitaxial layer, N-type isolation layers, oxide isolation layers, and a guard ring structure with specific well configurations and diffusion layers to reduce parasitic current by controlling hole and electron flow, enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a guard ring structure is added to increase breakdown voltage, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
The guard ring structure employs nested sub-wells (first, second, and third sub-wells) within the third well, creating a hierarchical nested configuration. This nesting approach allows multiple functional regions to be integrated within a compact structure, achieving high breakdown voltage while controlling device complexity through spatial efficiency.
Solution Approach 2:
The guard ring structure is segmented into multiple conductivity type regions (N-type first sub-well, P-type second sub-well, N-type third sub-well) arranged in alternating sequence. This segmentation creates multiple depletion regions that collectively enhance breakdown voltage while distributing the structural complexity across functional segments.
2Object-generated harmful factors
If the guard ring structure is designed with multiple sub-wells to suppress parasitic current, then parasitic current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
Different sub-wells are designed with specific local properties: the second sub-well has a greater depth than the first sub-well to optimize hole capture, while the third sub-well provides additional N-type region for electrical connection. This localized quality differentiation suppresses parasitic current through optimized carrier capture at specific locations without requiring uniform high precision across all structures.
Solution Approach 2:
The P-type buried layer acts as an intermediary between the second sub-well and the N-type isolation layer, facilitating controlled electrical connection while maintaining the guard ring's isolation function. This intermediary structure reduces parasitic current by providing a defined path for carrier collection without requiring extremely precise alignment between the second sub-well and isolation layer.
3Reliability
If deep wells are added between the first well and isolation layer to improve breakdown voltage, then breakdown voltage is improved, but device complexity increases
Solution Approach 1:
Deep wells are introduced as an additional dimensional feature extending vertically between the first well and the N-type isolation layer. This dimensional extension creates additional depletion regions in the vertical dimension, enhancing breakdown voltage without requiring additional horizontal structures, thereby managing complexity through spatial efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the breakdown voltage and reduces parasitic current, enabling stable operation of high voltage power diodes in high current applications, improving efficiency and preventing latch-up.
Implementation Method 1
The third well includes a first sub-well of N-type conductivity, a second sub-well of P-type conductivity and an third sub-well of N-type conductivity which are arranged in a horizontal direction to define an NPN structure. When a forward voltage is applied between the anode terminal and the cathode terminal, a hole current flows toward the P-sub region through the formed the first transistor of PNP type.
Implementation Method 2
the second sub-well 171b of the P-type conductivity may capture the hole current to reduce the hole current which flows toward the P-sub region so that the parasitic current flowing in the P-sub region have may decrease
Implementation Method 3
the P-type diffusion layer may suppress electrons from flowing from the guard ring terminal into the first sub-well
Implementation Method 4
oxide isolation layer provided at an upper surface of the epitaxial layer, the oxide isolation layer defining the epitaxial layer into an anode region and a cathode region
Data Source
AI summary
A high voltage power diode includes a P-type semiconductor substrate, a P-type epitaxial layer provided on the semiconductor substrate, an N-type isolation layer provided at a lower portion of the epitaxial layer, the isolation layer extending in a horizontal direction, oxide isolation layer provided at an upper surface of the epitaxial layer, the oxide isolation layer defining the epitaxial layer into an anode region and a cathode region, an first well of N-type conductivity, and a second well of P-type conductivity are provided on the upper surface of the epitaxial layer, a guard ring structure provided on the upper surface of the epitaxial layer and spaced apart from the second well in a horizontal direction, the guard ring structure including a third well having a first sub-well of N-type conductivity, a second sub-well of P-type conductivity and an third sub-well of N-type conductivity which are arranged in a horizontal direction, and a guard ring terminal electrically connected to the anode terminal.