High-Voltage ESD Clamp Circuit With Stacked Transistor Discharge Paths
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Solution Overview
Problem
Electrostatic discharge (ESD) sensitive devices can experience latent defects after an ESD event, leading to intermittent or permanent failures that may not be detected by normal inspection, posing a risk of catastrophic failure.
Innovation Solution
An ESD protection circuit is designed with a stack of transistors and an ESD clamp that enables a parasitic NPN bipolar transistor to discharge current via gate-induced drain leakage, reducing the voltage across ESD-sensitive circuits during an ESD event by tracking ground voltage, thereby enhancing protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits are used, then basic ESD protection is provided, but the voltage across ESD-sensitive circuits during ESD events is not sufficiently reduced, leading to latent defects and potential failures
Solution Approach 1:
The ESD protection function is segmented into multiple parallel discharge paths: a first discharge path through a first transistor to ground, and a second discharge path through a second transistor to a voltage node. This segmentation allows the circuit to handle different voltage levels and discharge currents more effectively, reducing the voltage stress on protected circuits during ESD events.
Solution Approach 2:
A third transistor is introduced as an intermediary element coupled between the first and second transistors. This intermediary transistor acts as a controlled switch that manages current distribution between the two discharge paths, optimizing the discharge effectiveness and further reducing voltage stress on ESD-sensitive circuits during electrostatic discharge events.
2Reliability
If higher protection current is discharged through the substrate, then voltage reduction during ESD events is improved, but the device complexity increases due to additional transistors and control circuits
Solution Approach 1:
The protection circuit uses self-service mechanisms where the transistors automatically activate and regulate based on voltage conditions without external control signals. The third transistor's gate is coupled to its drain, creating a self-regulating structure that automatically adjusts current distribution between discharge paths based on the ESD event characteristics, eliminating the need for additional control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the voltage across ESD-sensitive circuits during ESD events, improving protection and preventing failures by discharging more current through the substrate, compared to embodiments lacking this design.
Implementation Method 1
the mechanism by which the parasitic NPN transistor discharges current is gate-induced drain leakage (GIDL), which is dependent on the voltage at the gate of the first transistor
Data Source
AI summary
In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.