High-Voltage ESD Triggering Circuit to Prevent Premature Protection
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Solution Overview
Problem
Traditional electrostatic discharge (ESD) protection circuits in semiconductor devices with high voltage circuits often prematurely trigger due to inability to handle high voltages, leading to inoperability of high voltage circuits.
Innovation Solution
Incorporating a high voltage ESD triggering circuit that can handle high voltages, preventing premature triggering of ESD protection during normal operation and ensuring protection from high voltage ESD events by using a PNP ESD triggering device with specific doping configurations and structural arrangements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If ESD protection is activated during normal high voltage operation, then device protection is provided, but high voltage circuits become inoperable
Solution Approach 1:
The patent utilizes parameter changes by designing the ESD triggering circuit with specific voltage threshold characteristics through controlled doping profiles. The n-doped barrier regions and p-doped wells create a breakdown voltage threshold that is higher than normal operating voltages but lower than ESD event voltages. This parameter differentiation enables the circuit to remain operational during normal high voltage conditions while automatically triggering protection only when ESD events exceed the threshold.
2Device complexity
If traditional ESD triggering circuitry is used, then simple circuit design is maintained, but premature ESD triggering occurs
Solution Approach 1:
The patent introduces an intermediary high voltage ESD triggering circuit that acts as a mediator between the high voltage circuits and the ESD protection circuit. This intermediary circuit contains specialized components (n-doped barrier regions, p-doped wells with specific configurations) that translate high voltage conditions into appropriate triggering signals. The intermediary structure enables accurate discrimination between normal operation and ESD events without requiring direct modification of the high voltage circuits themselves.
Data Source
AI summary
A semiconductor device may include a electrostatic discharge (ESD) protection circuit and a high voltage ESD triggering circuit that is configured to trigger ESD protection for high voltage circuits of the semiconductor device. The high voltage ESD triggering circuit may be implemented by one or more of the example implementations of high voltage ESD triggering circuits described herein. The example implementations of high voltage ESD triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of and/or prevents premature triggering of ESD protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage ESD events.


