High-Voltage FET Gate Structure to Prevent CMP Erosion
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the complexity and inefficiency in forming high voltage input/output (I/O) field effect transistors (FETs) due to the scaling down of semiconductor devices, which leads to issues like gate electrode erosion and non-uniform thickness during chemical mechanical planarization (CMP), affecting the performance and reliability of I/O FETs.
Innovation Solution
The method involves forming I/O FETs with polysilicon gate electrodes and silicon oxide gate dielectrics concurrently with non-I/O FETs having metal gate electrodes and high-k gate dielectrics, where the polysilicon gate electrode provides resilience to CMP dishing, allowing for larger I/O FETs with uniform thickness and compatibility with both planar and non-planar transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal gate electrodes and high-k gate dielectrics are used for non-I/O FETs, then device scaling and performance are improved, but gate electrode erosion and non-uniform thickness occur during CMP processing
Solution Approach 1:
The patent segments the substrate into different regions (I/O region and non-I/O region) with different gate electrode materials. The I/O region uses polysilicon gate electrodes that are resistant to CMP erosion, while the non-I/O region uses metal gate electrodes for high performance. This segmentation allows each region to have optimized characteristics for its specific function.
Solution Approach 2:
The patent applies different material properties to different locations on the substrate. Polysilicon gate electrodes with high CMP resistance are placed in the I/O region where high voltage processing requires robust structures, while metal gate electrodes are placed in the non-I/O region where performance is prioritized. This local differentiation resolves the contradiction between CMP uniformity and electrode integrity.
2Productivity
If device dimensions are scaled down to increase storage capacity and processing speed, then performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent creates a universal fabrication process that can handle both polysilicon and metal gate electrodes using the same sequence of steps. The process includes forming both types of gate electrodes concurrently, followed by a single CMP step that selectively removes excess material from both regions. This multi-functional approach allows device scaling and performance improvement without proportionally increasing manufacturing complexity.
3Reliability
If I/O FETs are made larger to prevent CMP erosion, then gate electrode integrity is improved, but device area increases
Solution Approach 1:
The patent changes the material parameter of the gate electrode in the I/O region from metal to polysilicon. This material parameter change increases resistance to CMP erosion, allowing the I/O FETs to maintain their required dimensions without excessive erosion. The parameter change enables reliable high-voltage I/O devices without requiring larger device areas.
Data Source
AI summary
The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.