High-Voltage FET Structure for FinFET Process Integration
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Solution Overview
Problem
Existing semiconductor device fabrication processes cannot integrate high-voltage planar field-effect transistors into a process flow forming fin-type field-effect transistors without impacting the formation of the fin-type transistors.
Innovation Solution
A semiconductor device structure and method that include a layer stack with a first and second dielectric layer, a metal gate positioned laterally between source/drain regions, and a contact extending through the layer stack to one of the source/drain regions, enabling the formation of high-voltage field-effect transistors without disrupting the process flow for fin-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-voltage planar field-effect transistors are integrated into a process flow forming fin-type field-effect transistors, then high voltage handling capability is achieved, but the formation of fin-type transistors is impacted
Solution Approach 1:
The patent divides the semiconductor substrate into distinct regions: a first region for fin-type field-effect transistors and a second region for planar high-voltage field-effect transistors. This spatial segmentation allows each transistor type to be formed with its own optimized process parameters without interfering with the other, resolving the contradiction between achieving high voltage capability and maintaining fin-type transistor formation quality
Solution Approach 2:
The patent applies different process conditions to different regions of the substrate. The planar high-voltage transistors in the second region receive specialized processing (such as different doping concentrations, gate structure formations, and dielectric layer configurations) tailored to their high voltage requirements, while the fin-type transistors in the first region maintain their standard formation process, thus achieving local optimization without compromising overall manufacturing
Data Source
AI summary
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate and a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer is positioned between the second dielectric layer and the semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a metal gate on the layer stack laterally between the first source/drain region and the second source/drain region. The second dielectric layer is positioned between the metal gate and the first dielectric layer. A contact extends through the layer stack to the first source/drain region.