High-Voltage FinFET Isolation Layout for Mixed-Voltage Fabrication
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Solution Overview
Problem
The challenge lies in fabricating high voltage devices, such as I/O devices and ADCs, which often remain planar while core devices have evolved into multi-gate structures like FinFETs. This discrepancy in design and manufacturing processes leads to complications in forming isolation structures and achieving uniform feature sizes and insulation requirements across different device areas on the same workpiece.
Innovation Solution
The proposed solution involves forming FinFETs with isolation structures that include an isolation gate structure on a dielectric material within a fin cut trench. This approach allows for the separate formation of fin cut trenches in core and high voltage device areas using different lithographic processes, enabling the creation of isolation structures with varying dimensions to accommodate the distinct requirements of each device type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar high voltage devices are replaced with multi-gate high voltage devices, then device performance and integration are improved, but fabrication complexity and space requirements increase due to isolation structures
Solution Approach 1:
The workpiece is divided into distinct first and second areas with different lithographic processes. The first area uses a first lithographic process for core devices, while the second area uses a second lithographic process for high voltage devices, allowing each region to be optimized independently for its specific device type and requirements.
Solution Approach 2:
Different lithographic processes are applied to different areas of the workpiece based on local requirements. The first area receives a first lithographic process suitable for core devices, while the second area receives a second lithographic process optimized for high voltage devices, enabling localized optimization of fabrication parameters.
2Manufacturing precision
If different lithographic processes are used for core and high voltage device areas, then manufacturing flexibility and device quality are improved, but process complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct lithographic steps for different areas. A first lithographic process is performed on the first area, followed by a second lithographic process on the second area, allowing each process to be independently optimized and controlled for its specific requirements.
Solution Approach 2:
The first lithographic process is performed as a preliminary action on the first area before the second lithographic process is applied to the second area. This sequential approach allows proper sequencing and integration of different fabrication processes while maintaining overall process control.
Data Source
AI summary
Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.