High-Voltage FinFET LDMOS Structure for Voltage Tolerance
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Solution Overview
Problem
Conventional high-voltage MOSFET devices with LDMOS structure face challenges in increasing drain voltage tolerance while maintaining component density, as widening the distance between the drain and source reduces device density.
Innovation Solution
A high-voltage FinFET device with an LDMOS structure is designed, featuring a FIN structure with a first-type and second-type well region, a trench separating the FIN structure into parts, a shallow trench isolation structure, and a replacement metal gate process to form doped layers and gates, which widens the distance between the drain and source without reducing component density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between the drain and source is widened to increase voltage tolerance, then the bearable voltage of the drain is improved, but the component density is reduced
Solution Approach 1:
The patent introduces a vertical FinFET structure where the drain and source are separated in the vertical dimension through the fin depth, rather than only in the horizontal plane. This allows voltage tolerance to be improved through increased vertical separation while maintaining horizontal space efficiency for high component density.
Solution Approach 2:
The patent embeds the LDMOS structure within the FinFET architecture, nesting the lateral diffusion region inside the vertically-oriented fin structure. This nested configuration allows both structures to coexist in a compact footprint, achieving high voltage tolerance without sacrificing component density.
2Reliability
If the distance between the drain and source is increased to enhance breakdown strength, then the device reliability is improved, but the device area is increased
Solution Approach 1:
The patent utilizes the vertical dimension of the FinFET structure to achieve the required drain-source separation for high breakdown strength. By extending the separation vertically through the fin depth rather than horizontally across the device area, the patent maintains compact device footprints while achieving enhanced reliability.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the FinFET structure provides vertical separation in the active region for high breakdown strength, while the LDMOS lateral diffusion region provides additional voltage tolerance locally. This localized optimization allows high reliability without excessive overall device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the drain's voltage tolerance by widening the distance between the drain and source doped layers while maintaining device density, enhancing the bearable voltage without compromising component packing.
Implementation Method 1
a first ion implantation process, to form a drain doped layer on the first part above the first type well region, and forms a source doped layer on the second part above the second type well region
Implementation Method 2
growing a epitaxial material layer on the openings
Data Source
AI summary
A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.