High-Voltage FinFET Gate Structure to Avoid CMP Erosion
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in the complexity of scaling down semiconductor devices, particularly in forming high-voltage input/output (I/O) field effect transistors (FETs) with metal gate electrodes, which face issues like gate electrode erosion and non-uniform thickness due to chemical mechanical planarization (CMP), degrading performance and reliability.
Innovation Solution
The method involves forming I/O FETs with polysilicon gate electrodes and silicon oxide gate dielectrics concurrently with non-I/O FETs having metal gate electrodes and high-k gate dielectrics, where the polysilicon gate electrodes provide resilience to CMP dishing, allowing for larger I/O FETs with uniform thickness and compatibility with both planar and non-planar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal gate electrodes are used in high-voltage I/O FETs, then device performance is improved, but gate electrode erosion and non-uniform thickness occur due to CMP
Solution Approach 1:
The patent applies different gate electrode materials to different regions: polysilicon for high-voltage I/O FETs where CMP resistance is critical, and metal gates for standard FETs where performance is prioritized. This local differentiation resolves the contradiction by matching material properties to specific application requirements.
Solution Approach 2:
The patent uses polysilicon gate electrodes as a sacrificial or protective structure during CMP processes. The polysilicon layer can be selectively removed or retained based on process requirements, serving as a disposable protective element that prevents damage to underlying structures during manufacturing.
2Productivity
If device dimensions are scaled down, then storage capacity and processing speed are improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameter (using polysilicon instead of metal) for gate electrodes in specific regions to simplify the CMP process. This parameter change allows standard CMP processes to be used without requiring complex process modifications, thereby enabling scaling while controlling manufacturing complexity.
3Reliability
If I/O FET size is increased, then high-voltage handling capability is improved, but CMP-induced erosion and dishing worsen
Solution Approach 1:
The patent converts the harmful effect of CMP on large I/O FET gates into a benefit by using polysilicon as a protective layer. The polysilicon gate electrode is more resistant to CMP damage, and any erosion that does occur can be compensated for in the design, thereby enabling larger I/O FETs to be manufactured with acceptable precision.
Data Source
AI summary
The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.