High-Voltage Transistor Gate Layout With Shared Dielectric Layer
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Solution Overview
Problem
Existing semiconductor devices face challenges in sustaining high voltages while adhering to the downsizing requirements of advanced processes, as the gate structure thickness exceeds the dielectric layer, leading to insulation issues and complex manufacturing processes.
Innovation Solution
The implementation of an insulating layer that functions as both a gate oxide for high-voltage transistors and a dielectric layer for low-voltage transistors, allowing the integration of both types without additional complexity, using a patterned conductive layer as part of the interconnection layer for routing, eliminating the need for spacers and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure thickness is increased to sustain high voltages, then the voltage sustaining capability is improved, but the gate structure thickness exceeds the dielectric layer thickness leading to insulation issues and complex manufacturing processes
Solution Approach 1:
The dielectric layer is designed to serve dual functions: as the gate oxide for high-voltage transistors and as the dielectric layer for low-voltage transistors. This multi-functionality eliminates the need for separate gate oxide formation processes and resolves the contradiction by enabling high voltage sustainment without adding manufacturing complexity
Solution Approach 2:
The patent combines the gate oxide formation and dielectric layer formation into a single process step. The same dielectric layer material and deposition process are used for both high-voltage and low-voltage transistor regions, merging what would traditionally be separate processes into one unified operation
2Manufacturing precision
If separate gate oxide and dielectric layer formation processes are used for high-voltage and low-voltage transistors, then each transistor type can be optimized, but the manufacturing process becomes more complex
Solution Approach 1:
A single dielectric layer is formed that serves as the gate oxide for high-voltage transistors and as the dielectric layer for low-voltage transistors simultaneously. This universal approach maintains manufacturing precision for both transistor types while eliminating the need for separate formation processes
Solution Approach 2:
The dielectric layer is formed with different local properties in different regions: in high-voltage transistor regions, it functions as gate oxide with specific thickness and material properties, while in low-voltage transistor regions, it functions as the dielectric layer. This local differentiation achieves optimization for each transistor type through a single unified process
Data Source
AI summary
A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.