High Voltage Device Gate Structure for Metal Ion Diffusion Control
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Solution Overview
Problem
The reliability of high voltage devices in integrated circuits is compromised as they shrink in size, particularly due to concerns with high-κ metal gate reliability, which can lead to metal ion diffusion issues when eliminated, impacting device operation.
Innovation Solution
The method involves fabricating integrated circuits without high-κ metal gates by forming a semiconductor substrate with device wells, gate dielectrics, and shallow trench isolation structures, where a second gate electrode layer is deposited over an insulating dielectric layer, and contacts are formed to prevent metal ion diffusion, utilizing existing processing stages for both memory cells and high voltage devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of high voltage devices is decreased, then the integration density and performance of the integrated circuit is improved, but the reliability of the high-κ metal gate becomes compromised
Solution Approach 1:
The patent removes the high-κ metal gate layer from the device structure, extracting the problematic component that causes metal ion diffusion issues. This is achieved by modifying the gate stack formation process to deposit only the gate dielectric and gate electrode layers, deliberately omitting the high-κ metal gate deposition step, thereby eliminating the reliability issue while maintaining device functionality
Solution Approach 2:
The patent introduces an intermediate protective layer between the gate electrode and the contact region. This intermediate layer acts as a barrier that prevents metal ion diffusion from the contact through the gate electrode into the gate dielectric, solving the reliability issue without requiring removal of the high-κ metal gate or increasing device size
2Reliability
If the high-κ metal gate is eliminated to improve reliability, then metal ion diffusion is prevented, but additional processing stages are required
Solution Approach 1:
The patent combines the formation of the protective intermediate layer with the existing gate electrode deposition process. The protective layer is deposited as part of the same processing sequence used to form the gate electrode, merging two functions into a single integrated process step rather than adding a separate processing stage
Solution Approach 2:
The patent designs the gate electrode layer to serve multiple functions: it provides the primary gate control function and simultaneously acts as a barrier layer to prevent metal ion diffusion. This multi-functionality eliminates the need for separate protective layers or additional processing stages, as the gate electrode itself fulfills both roles
3Productivity
If the size of high voltage devices is decreased, then the integration density is improved, but metal ion diffusion from contact through gate electrode into gate dielectric occurs
Solution Approach 1:
The patent introduces an intermediate protective layer between the gate electrode and the contact region. This intermediate layer acts as a barrier that prevents metal ion diffusion from the contact through the gate electrode into the gate dielectric, solving the reliability issue without requiring removal of the high-κ metal gate or increasing device size
Solution Approach 2:
The patent employs a composite gate structure consisting of multiple material layers with different properties. The gate stack includes the gate dielectric, gate electrode, and protective intermediate layer, where each material is selected for its specific function: the gate dielectric for electrical isolation, the gate electrode for control, and the intermediate layer for diffusion barrier properties, creating a composite structure that prevents metal ion diffusion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of high voltage devices by eliminating high-κ metal gate-related issues, allowing for the use of conventional gate dielectrics and preventing metal ion diffusion, while maintaining the integration of memory cells and high voltage devices without additional processing stages.
Implementation Method 1
a gate dielectric (e.g., a gate oxide) overlying the device well
Implementation Method 2
a shallow trench isolation structure within the substrate between the first device well and the second device well
Data Source
AI summary
Methods of fabricating integrated circuits and integrated circuits fabricated by those methods are provided. In an exemplary embodiment, a method includes providing a substrate having a first and second device wells, a gate dielectric overlying the first and second device wells, a first gate electrode layer overlying the gate dielectric, and a shallow trench isolation structure between the first and second device wells. An insulating dielectric layer is formed only partially overlying the first gate electrode layer. A second gate electrode material is deposited overlying at least the insulating dielectric layer to form a second gate electrode layer. The layers are patterned to form a second gate structure overlying the second device well. A contact is formed on the second gate electrode layer of the second gate structure with the contact overlying dielectric material of at least one of the insulating dielectric layer or the shallow trench isolation structure.